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v850es/ke1 32-bit single-chip microcontrollers hardware printed in japan document no. u16892ej1v0ud00 (1st edition) date published may 2004 n cp(k) preliminary user?s manual pd703207 pd703207y pd70f3207h pd70f3207hy 2004
preliminary user?s manual u16892ej1v0ud 2 [memo]
preliminary user?s manual u16892ej1v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. caution: windows and windows nt are either re gistered trademarks or trademar ks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. superflash is a registered trademark of s ilicon storage technology, inc. in several countries including the united states and japan.
preliminary user?s manual u16892ej1v0ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. ? ? ? ? ? ? ?
preliminary user?s manual u16892ej1v0ud 5 regional information ? ? ? ? ? ? ? ? ? ? ? ?
preliminary user?s manual u16892ej1v0ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/ke1 and design applicati on systems using these products. the target products are as follows. ? ? ? ? ? ? ? ? ? ? ?
preliminary user?s manual u16892ej1v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/ke1 document name document no. v850es architecture user?s manual u15943e v850es/ke1 hardware user?s manual this manual documents related to developm ent tools (user?s manuals) document name document no. operation u16053e c language u16054e ca850 ver. 2.50 c compiler package assembly language u16042e pm plus ver. 5.20 u16934e id850qb ver. 2.80 integrated debugger operation u16973e operation u16906e sm plus ver. 1.00 system simulator user open interface u16907e basics u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e basics u13773e installation u13774e rx850 pro ver. 3.15 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.20 system performance analyzer u14410e pg-fp4 flash memory programmer u15260e
preliminary user?s manual u16892ej1v0ud 8 contents chapter 1 introduction...................................................................................................... ............15 1.1 k1 family product lineup................................................................................................... ...... 15 1.1.1 v850es/kx1+, v850es/ kx1 products lineup................................................................................. 1 5 1.1.2 78k0/kx1+, 78k0/k x1 products lineup ...................................................................................... .... 18 1.2 features ................................................................................................................... ................... 21 1.3 applications............................................................................................................... ................. 22 1.4 ordering information ....................................................................................................... .......... 22 1.5 pin configuration (top view)............................................................................................... ..... 23 1.6 function block configuration......................................... ...................................................... .... 26 1.7 overview of functions...................................................................................................... ......... 30 chapter 2 pin functions .................................................................................................... ............31 2.1 list of pin functions...................................................................................................... ............ 31 2.2 pin i/o circuits and recommende d connection of unused pins......................................... 35 2.3 pin i/o circuits........................................................................................................... ................. 37 chapter 3 cpu functions.................................................................................................... ...........39 3.1 features ................................................................................................................... ................... 39 3.2 cpu register set........................................................................................................... ............. 40 3.2.1 program re gister set ..................................................................................................... ................. 41 3.2.2 system r egister set ...................................................................................................... .................. 42 3.3 operating modes ............................................................................................................ ............ 48 3.4 address space .............................................................................................................. ............. 49 3.4.1 cpu addr ess s pace ........................................................................................................ ............... 49 3.4.2 wraparound of cpu address space .......................................................................................... .... 50 3.4.3 memo ry map............................................................................................................... ................... 51 3.4.4 areas .................................................................................................................... ......................... 53 3.4.5 recommended us e of addres s space ......................................................................................... .. 55 3.4.6 peripheral i/o registers ................................................................................................. ................. 57 3.4.7 special registers ........................................................................................................ .................... 63 3.4.8 c autio ns................................................................................................................. ........................ 66 chapter 4 port functions ................................................................................................... .........69 4.1 features ................................................................................................................... ................... 69 4.2 basic port configuration................................................................................................... ........ 69 4.3 port configurat ion......................................................................................................... ............. 70 4.3.1 port 0 ................................................................................................................... .......................... 75 4.3.2 port 3 ................................................................................................................... .......................... 77 4.3.3 port 4 ................................................................................................................... .......................... 82 4.3.4 port 5 ................................................................................................................... .......................... 84 4.3.5 port 7 ................................................................................................................... .......................... 87 4.3.6 port 9 ................................................................................................................... .......................... 88 4.3.7 port cm.................................................................................................................. ........................ 94 4.3.8 port dl.................................................................................................................. ......................... 95 4.4 block diagrams ............................................................................................................. ............. 96
preliminary user?s manual u16892ej1v0ud 9 4.5 port register setting when al ternate function is used ..................................................... 115 4.6 cautions................................................................................................................... ................. 119 4.6.1 cautions on bit manipulation inst ruction for port n register (pn) ...................................................119 4.6.2 hysteresis characteri stics ............................................................................................... ..............120 chapter 5 clock generation function ...............................................................................121 5.1 overview ................................................................................................................... ................ 121 5.2 configuration.............................................................................................................. .............. 122 5.3 register................................................................................................................... .................. 124 5.4 operation .................................................................................................................. ................ 128 5.4.1 operation of each clock .................................................................................................. ..............128 5.4.2 clock output function .................................................................................................... ................128 5.4.3 external clo ck input f unction ............................................................................................ .............128 5.5 pll function ............................................................................................................... ............. 129 5.5.1 ov ervi ew ................................................................................................................. .....................129 5.5.2 r egist er ................................................................................................................. .......................129 5.5.3 usage .................................................................................................................... .......................130 chapter 6 16-bit timer/event counter p (tmp) .................................................................131 6.1 overview ................................................................................................................... ................ 131 6.2 functions .................................................................................................................. ................ 131 6.3 configuration.............................................................................................................. .............. 132 6.4 registers.................................................................................................................. ................. 134 6.5 operation .................................................................................................................. ................ 145 6.5.1 interval timer mode (tp0 md2 to tp0md0 bits = 000).................................................................. 146 6.5.2 external event count mode (t p0md2 to tp0md0 bits = 001) ......................................................156 6.5.3 external trigger pulse output mode (tp0md2 to tp0m d0 bits = 010) ..........................................164 6.5.4 one-shot pulse output mode (t p0md2 to tp0md0 bits = 011) ...................................................176 6.5.5 pwm output mode (tp0md2 to tp0md0 bi ts = 100) ...................................................................183 6.5.6 free-running timer mode (tp0 md2 to tp0md0 bits = 101) ......................................................... 192 6.5.7 pulse width measurement mode (tp0md2 to tp0md0 bits = 110) .............................................209 6.5.8 timer output operations.................................................................................................. ..............215 6.6 eliminating noise on capture trig ger input pin (tip0a)...................................................... 216 6.7 cautions................................................................................................................... ................. 218 chapter 7 16-bit timer/event counter 0..............................................................................219 7.1 functions .................................................................................................................. ................ 219 7.2 configuration.............................................................................................................. .............. 220 7.3 registers.................................................................................................................. ................. 225 7.4 operation .................................................................................................................. ................ 232 7.4.1 operation as interval timer .............................................................................................. .............232 7.4.2 ppg output operation ..................................................................................................... ..............234 7.4.3 pulse widt h measur ement .................................................................................................. ..........238 7.4.4 operation as ex ternal event count er...................................................................................... .......247 7.4.5 square-wave output oper ation............................................................................................. .........250 7.4.6 one-shot puls e output op eration .......................................................................................... ........253 7.4.7 c autio ns ................................................................................................................. ......................256
preliminary user?s manual u16892ej1v0ud 10 chapter 8 8-bit timer/event counter 5 ............................................................................... 260 8.1 functions .................................................................................................................. ................ 260 8.2 configuration.............................................................................................................. .............. 261 8.3 registers .................................................................................................................. ................. 264 8.4 operation .................................................................................................................. ................ 267 8.4.1 operation as interval timer.............................................................................................. ............. 267 8.4.2 operation as ex ternal event count er ...................................................................................... ...... 269 8.4.3 square-wave output oper ation............................................................................................. ........ 270 8.4.4 8-bit pwm output oper ation ............................................................................................... .......... 272 8.4.5 operation as inte rval timer (16 bits).................................................................................... ......... 275 8.4.6 operation as external event counter (16 bits) ............................................................................ .. 277 8.4.7 square-wave output oper ation (16-bit resoluti on) ........................................................................ 2 78 8.4.8 c autio ns................................................................................................................. ...................... 279 chapter 9 8-bit timer h ................................................................................................... ............ 280 9.1 functions .................................................................................................................. ................ 280 9.2 configuration.............................................................................................................. .............. 280 9.3 registers .................................................................................................................. ................. 283 9.4 operation .................................................................................................................. ................ 287 9.4.1 operation as interval timer/square wave output ........................................................................... 287 9.4.2 pwm output mode oper ation ................................................................................................ ....... 290 9.4.3 carrier generat or mode o peratio n......................................................................................... ....... 296 chapter 10 interval timer, watch timer ........................................................................... 303 10.1 interval timer brg........................................................................................................ ........... 303 10.1.1 f uncti ons ............................................................................................................... ...................... 303 10.1.2 config uration ........................................................................................................... .................... 303 10.1.3 regi sters............................................................................................................... ....................... 305 10.1.4 oper ation ............................................................................................................... ...................... 307 10.2 watch timer............................................................................................................... ............... 308 10.2.1 f uncti ons ............................................................................................................... ...................... 308 10.2.2 config uration ........................................................................................................... .................... 308 10.2.3 r egist er ................................................................................................................ ....................... 309 10.2.4 oper ation ............................................................................................................... ...................... 311 10.3 cautions .................................................................................................................. .................. 312 chapter 11 watchdog timer functions .............................................................................. 314 11.1 watchdog timer 1 .......................................................................................................... .......... 314 11.1.1 f uncti ons ............................................................................................................... ...................... 314 11.1.2 config uration ........................................................................................................... .................... 316 11.1.3 regi sters............................................................................................................... ....................... 316 11.1.4 oper ation ............................................................................................................... ...................... 318 11.2 watchdog timer 2 .......................................................................................................... .......... 320 11.2.1 f uncti ons ............................................................................................................... ...................... 320 11.2.2 config uration ........................................................................................................... .................... 321 11.2.3 regi sters............................................................................................................... ....................... 321 11.2.4 oper ation ............................................................................................................... ...................... 323
preliminary user?s manual u16892ej1v0ud 11 chapter 12 real-time output function (rto)....................................................................324 12.1 function .................................................................................................................. .................. 324 12.2 configuration............................................................................................................. ............... 325 12.3 registers................................................................................................................. .................. 326 12.4 operation ................................................................................................................. ................. 328 12.5 usage ..................................................................................................................... ................... 329 12.6 cautions.................................................................................................................. .................. 329 12.7 security function......................................................................................................... ............ 330 chapter 13 a/d converter ................................................................................................... .......332 13.1 functions ................................................................................................................. ................. 332 13.2 configuration............................................................................................................. ............... 333 13.3 registers................................................................................................................. .................. 335 13.4 operation ................................................................................................................. ................. 342 13.4.1 basic operation......................................................................................................... ....................342 13.4.2 a/d conver sion oper ation ................................................................................................ .............343 13.4.3 power fail m onitoring fu nction.......................................................................................... .............343 13.5 cautions.................................................................................................................. .................. 345 13.6 how to read a/d converter char acteristics table .............................................................. 350 chapter 14 asynchronous serial interface (uart) .....................................................354 14.1 features .................................................................................................................. .................. 354 14.2 configuration............................................................................................................. ............... 355 14.3 registers................................................................................................................. .................. 357 14.4 interrupt requests ........................................................................................................ ........... 363 14.5 operation ................................................................................................................. ................. 364 14.5.1 data format............................................................................................................. ......................364 14.5.2 transmi t operat ion...................................................................................................... ..................365 14.5.3 continuous trans mission op eration ....................................................................................... .......367 14.5.4 receive operat ion....................................................................................................... ..................371 14.5.5 recept ion error......................................................................................................... ....................372 14.5.6 parity types and corresponding operatio n ................................................................................ ....374 14.5.7 receive dat a noise filter ............................................................................................... ................375 14.6 dedicated baud rate generator n (brgn).............. .............................................................. 376 14.6.1 baud rate generator n (brgn) conf igurat ion .............................................................................. ..376 14.6.2 serial cl ock gener ation ................................................................................................. ................377 14.6.3 baud rate setting ex ample ............................................................................................... .............380 14.6.4 allowable baud rate range during reception .............................................................................. ...381 14.6.5 transfer rate during continuous transmi ssion............................................................................ ...383 14.7 cautions.................................................................................................................. .................. 383 chapter 15 clocked serial interface 0 (csi0).................................................................384 15.1 features .................................................................................................................. .................. 384 15.2 configuration............................................................................................................. ............... 385 15.3 registers................................................................................................................. .................. 388 15.4 operation ................................................................................................................. ................. 397 15.4.1 transmission/reception completion in terrupt request si gnal (intcs i0n) ......................................397 15.4.2 single tr ansfer mode .................................................................................................... ................399
preliminary user?s manual u16892ej1v0ud 12 15.4.3 continuous transfe r mode................................................................................................ ............ 402 15.5 output pins ............................................................................................................... ................ 410 chapter 16 i 2 c bus ......................................................................................................................... . 411 16.1 features .................................................................................................................. .................. 411 16.2 configuration............................................................................................................. ............... 414 16.3 registers ................................................................................................................. .................. 416 16.4 functions ................................................................................................................. ................. 429 16.4.1 pin conf iguration ....................................................................................................... ................... 429 16.5 i 2 c bus definitions and control methods ......................... ..................................................... 430 16.5.1 start conditi on......................................................................................................... ..................... 430 16.5.2 addr esses............................................................................................................... ..................... 431 16.5.3 transfer direct ion specif ication ........................................................................................ ............ 431 16.5.4 acknowled ge signal (ack) ................................................................................................ .......... 432 16.5.5 stop c onditio n .......................................................................................................... .................... 433 16.5.6 wait si gnal (w ait)...................................................................................................... ................. 434 16.6 i 2 c interrupt request signals (intiic0) .......................... ........................................................ 436 16.6.1 master dev ice operat ion................................................................................................. .............. 436 16.6.2 slave device operation (when receivin g slave address data (matc h with addr ess)) .................... 439 16.6.3 slave device operation (w hen receiving ex tension code) ............................................................ 443 16.6.4 operation with out communi cation......................................................................................... ....... 447 16.6.5 arbitration loss oper ation (operation as slave after arbitrat ion lo ss) ............................................ 447 16.6.6 operation when arbitrat ion loss occurs (no communicati on after arbitr ation lo ss) ....................... 449 16.7 interrupt request signal (intiic 0) generation timing and wait c ontrol........................... 454 16.8 address match detection method .......................................................................................... 45 5 16.9 error detection ........................................................................................................... .............. 455 16.10 extension code ........................................................................................................... ............. 456 16.11 arbitration .............................................................................................................. ................... 457 16.12 wakeup function .......................................................................................................... ........... 458 16.13 communication reservation ................................................................................................ .. 459 16.13.1 when communication reservation functi on is enabled (iicf0 .iicrsv0 bi t = 0) ........................... 459 16.13.2 when communication reservation function is disabled (iicf0 .iicrsv0 bi t = 1) .......................... 462 16.14 cautions ................................................................................................................. ................... 463 16.15 communication operations ................................................................................................. ... 463 16.15.1 master operati on 1..................................................................................................... .................. 463 16.15.2 master operati on 2..................................................................................................... .................. 465 16.15.3 slave operation........................................................................................................ .................... 466 16.16 timing of data communication ............................................................................................. . 469 chapter 17 interrupt/exception processing function............................................... 476 17.1 overview .................................................................................................................. ................. 476 17.1.1 f eatur es................................................................................................................ ....................... 476 17.2 non-maskable interrupts ................................................................................................... ...... 479 17.2.1 oper ation ............................................................................................................... ...................... 482 17.2.2 re store ................................................................................................................. ....................... 483 17.2.3 np flag ................................................................................................................. ........................ 484 17.3 maskable interrupts ....................................................................................................... .......... 485 17.3.1 oper ation ............................................................................................................... ...................... 485
preliminary user?s manual u16892ej1v0ud 13 17.3.2 re store ................................................................................................................. ........................487 17.3.3 priorities of maskable in terrupts ....................................................................................... ............488 17.3.4 interrupt contro l register (xxlcn) ...................................................................................... .............492 17.3.5 interrupt mask registers 0, 1, 3 (imr0, imr1, im r3) ....................................................................4 94 17.3.6 in-service priori ty register (ispr)..................................................................................... .............495 17.3.7 id flag ................................................................................................................. ..........................496 17.3.8 watchdog timer mode register 1 (wdtm1) .................................................................................. 497 17.4 external interrupt requ est input pins (nmi, intp0 to intp6) .... ......................................... 498 17.4.1 noise e liminat ion ....................................................................................................... ...................498 17.4.2 edge de tection.......................................................................................................... ....................498 17.5 software exceptions....................................................................................................... ......... 501 17.5.1 oper ation............................................................................................................... .......................501 17.5.2 re store ................................................................................................................. ........................502 17.5.3 ep flag................................................................................................................. .........................503 17.6 exception trap ............................................................................................................ ............. 504 17.6.1 ill egal opc ode .......................................................................................................... .....................504 17.6.2 debu g tr ap.............................................................................................................. ......................506 17.7 multiple interrupt servicing co ntrol ...................................................................................... 508 17.8 interrupt response time................................................................................................... ...... 510 17.9 periods in which interrupts are not acknowledge d by cpu ............................................. 511 17.10 cautions................................................................................................................. ................... 511 chapter 18 key interrupt function ......................................................................................512 18.1 function .................................................................................................................. .................. 512 18.2 register.................................................................................................................. ................... 513 chapter 19 standby function ................................................................................................ ...514 19.1 overview .................................................................................................................. ................. 514 19.2 registers................................................................................................................. .................. 517 19.3 halt mode ................................................................................................................. .............. 520 19.3.1 setting and op eration status ............................................................................................ .............520 19.3.2 releasin g halt mode ..................................................................................................... ............520 19.4 idle mode................................................................................................................. ................ 522 19.4.1 setting and op eration status ............................................................................................ .............522 19.4.2 releasin g idle mode ..................................................................................................... ..............522 19.5 stop mode ................................................................................................................. .............. 524 19.5.1 setting and op eration status ............................................................................................ .............524 19.5.2 releasin g stop mode ..................................................................................................... ............524 19.5.3 securing oscillation stabilizati on time when stop m ode is rel eased ...........................................526 19.6 subclock operation mode................................................................................................... .... 527 19.6.1 setting and op eration status ............................................................................................ .............527 19.6.2 releasing subc lock operat ion mode....................................................................................... ......527 19.7 sub-idle mode............................................................................................................. ............ 529 19.7.1 setting and op eration status ............................................................................................ .............529 19.7.2 releasing sub-idle mode................................................................................................. ...........529 chapter 20 reset function .................................................................................................. ......531 20.1 overview .................................................................................................................. ................. 531
preliminary user?s manual u16892ej1v0ud 14 20.2 configuration............................................................................................................. ............... 531 20.3 operation ................................................................................................................. ................. 532 chapter 21 rom correction function................................................................................. 535 21.1 overview .................................................................................................................. ................. 535 21.2 registers ................................................................................................................. .................. 536 21.3 rom correction operation and program flow ........... .......................................................... 537 chapter 22 flash memory .................................................................................................... ...... 539 22.1 features .................................................................................................................. .................. 539 22.2 memory configuration ...................................................................................................... ....... 540 22.3 functional outline........................................................................................................ ............ 541 22.4 rewriting by dedicated flash programmer ................ .......................................................... 543 22.4.1 programmi ng environ ment................................................................................................. .......... 543 22.4.2 communica tion mode ...................................................................................................... ............ 544 22.4.3 flash memo ry control .................................................................................................... .............. 548 22.4.4 selection of communicati on mode ......................................................................................... ...... 549 22.4.5 communicati on commands .................................................................................................. ....... 550 22.4.6 pin co nnection .......................................................................................................... ................... 551 22.5 rewriting by self programming............................................................................................. . 556 22.5.1 ov ervi ew................................................................................................................ ...................... 556 22.5.2 f eatur es................................................................................................................ ....................... 557 22.5.3 standard self programmi ng flow .......................................................................................... ........ 558 22.5.4 flash functi ons......................................................................................................... .................... 559 22.5.5 pin pr ocessing .......................................................................................................... ................... 559 22.5.6 internal resource s used ................................................................................................. .............. 560 chapter 23 electrical specifications (target).............................................................. 561 chapter 24 package drawings ................................................................................................ 581 appendix a development tools............................................................................................... 583 a.1 software package........................................................................................................... .......... 585 a.2 language processing software.... .......................................................................................... 5 85 a.3 control software ........................................................................................................... ........... 585 a.4 debugging tools (hardware) ................................................................................................. . 586 a.4.1 when using in-circuit emulator qb-v 850eskx1 h....................................................................... 586 a.5 debugging tools (software) ................................................................................................. .. 587 a.6 embedded software.......................................................................................................... ....... 588 a.7 flash memory writing tools ................................................................................................. .. 588 appendix b instruction set list ........................................................................................... .. 589 b.1 conventions................................................................................................................ .............. 589 b.2 instruction set (in alphabetical order) .................... .............................................................. 59 2 appendix c register index .................................................................................................. ....... 599
preliminary user?s manual u16892ej1v0ud 15 chapter 1 introduction 1.1 k1 family product lineup 1.1.1 v850es/kx1+, v850es/kx1 products lineup v850es/ke1 ? 64-pin plastic lqfp (10 10 mm, 0.5 mm pitch) ? 64-pin plastic tqfp (12 12 mm, 0.65 mm pitch) pd70f3207hy pd70f3207h single-power flash: 128 kb, ram: 4 kb pd703207y pd703207 mask rom: 128 kb, ram: 4 kb pd703210y pd703210 mask rom: 128 kb, ram: 4 kb pd703209y pd703209 mask rom: 96 kb, ram: 4 kb pd70f3210hy pd70f3210h single-power flash: 128 kb, ram: 6 kb pd70f3306y pd70f3306 single-power flash: 128 kb, ram: 6 kb pd70f3210y pd70f3210 two-power flash: 128 kb, ram: 6 kb pd703208y pd703208 mask rom: 64 kb, ram: 4 kb v850es/ke1+ pd70f3302y pd70f3302 single-power flash: 128 kb, ram: 4 kb pd703302y pd703302 mask rom: 128 kb, ram: 4 kb v850es/kf1 ? 80-pin plastic tqfp (12 12 mm, 0.5 mm pitch) ? 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) ? 100-pin plastic lqfp (14 14 mm, 0.5 mm pitch) ? 100-pin plastic qfp (14 20 mm, 0.65 mm pitch) pd70f3211hy pd70f3211h single-power flash: 256 kb, ram: 12 kb pd703211y pd703211 mask rom: 256 kb, ram: 12 kb v850es/kf1+ pd70f3308y pd70f3308 single-power flash: 256 kb, ram: 12 kb pd703308y pd703308 mask rom: 256 kb, ram: 12 kb pd703214y pd703214 mask rom: 128 kb, ram: 6 kb pd703213y pd703213 mask rom: 96 kb, ram: 4 kb pd70f3214hy pd70f3214h single-power flash: 128 kb, ram: 6 kb pd70f3311y pd70f3311 single-power flash: 128 kb, ram: 6 kb pd70f3214y pd70f3214 two-power flash: 128 kb, ram: 6 kb pd703212y pd703212 mask rom: 64 kb, ram: 4 kb v850es/kg1 pd70f3215hy pd70f3215h single-power flash: 256 kb, ram: 16 kb pd703215y pd703215 mask rom: 256 kb, ram: 16 kb v850es/kg1+ pd70f3313y pd70f3313 single-power flash: 256 kb, ram: 16 kb pd703313y pd703313 mask rom: 256 kb, ram: 16 kb ? 144-pin plastic lqfp (20 20 mm, 0.5 mm pitch) pd703217y pd703217 mask rom: 128 kb, ram: 6 kb pd703216y pd703216 mask rom: 96 kb, ram: 4 kb pd70f3217hy pd70f3217h single-power flash: 128 kb, ram: 6 kb pd70f3316y pd70f3316 single-power flash: 128 kb, ram: 6 kb pd70f3217y pd70f3217 two-power flash: 128 kb, ram: 6 kb v850es/kj1 pd70f3218hy pd70f3218h single-power flash: 256 kb, ram: 16 kb v850es/kj1+ pd70f3318y pd70f3318 single-power flash: 256 kb, ram: 16 kb
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 16 the function list of the v 850es/kx1+ is shown below. product name v850es/ke1+ v850es/kf1+ v850es/kg1+ v850es/kj1+ number of pins 64 pins 80 pins 100 pins 144 pins mask rom 128 ? ? 256 ? ? 256 ? ? ? flash memory ? 128 128 ? 256 128 ? 256 128 256 internal memory (kb) ram 4 6 12 6 16 6 16 supply voltage 2.7 to 5.5 v minimum instruction execution time 50 ns @20 mhz x1 input 2 to 10 mhz subclock 32.768 khz clock ring-osc 240 khz (typ.) cmos input 8 8 8 16 cmos i/o 43 59 76 112 port n-ch open-drain i/o 2 2 4 6 16-bit (tmp) 1 ch 1 ch 1 ch 1 ch 16-bit (tm0) 1 ch 2 ch 4 ch 6 ch 8-bit (tm5) 2 ch 2 ch 2 ch 2 ch 8-bit (tmh) 2 ch 2 ch 2 ch 2 ch interval timer 1 ch 1 ch 1 ch 1 ch watch 1 ch 1 ch 1 ch 1 ch wdt1 1 ch 1 ch 1 ch 1 ch timer wdt2 1 ch 1 ch 1 ch 1 ch rto 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch csi 2 ch 2 ch 2 ch 3 ch automatic transmit/receive 3-wire csi ? 1 ch 2 ch 2 ch uart 1 ch 1 ch 2 ch 2 ch uart supporting lin-bus 1 ch 1 ch 1 ch 1 ch serial interface i 2 c note 1 ch 1 ch 1 ch 2 ch address space ? 128 kb 3 mb 15 mb address bus ? 16 bits 22 bits 24 bits external bus mode ? multiplex only multiplex/separate dma controller ? ? 4 ch 4 ch 10-bit a/d converter 8 ch 8 ch 8 ch 16 ch 8-bit d/a converter ? ? 2 ch 2 ch external 9 9 9 9 interrupt internal 27 30 42 48 key return input 8 ch 8 ch 8 ch 8 ch reset pin provided poc 2.7 v or less fixed lvi 3.1 v/3.3 v 0.15 v or 3.5 v/3.7 v/3.9 v/4.1 v/4.3 v 0.2 v (selectable by software) clock monitor provided (monitor by ring-osc) wdt1 provided reset wdt2 provided rom correction 4 none regulator none provided standby function halt/idle/stop/sub-idle mode operating ambient temperature t a = ? 40 to +85 c note only in products with an i 2 c bus (y products). for the product name, refer to each user?s manual.
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 17 the function list of the v850es/kx1 is shown below. product name v850es/ke1 v850es/kf1 v850es/kg1 v850es/kj1 number of pins 64 pins 80 pins 100 pins 144 pins mask rom 128 ? 64/ 96 128 ? 256 ? 64/ 96 128 ? 256 ? 96/128 ? ? flash memory ? 128 ? ? 128 ? 256 ? ? 128 ? 256 ? 128 256 internal memory (kb) ram 4 4 6 12 4 6 16 6 16 supply voltage 2.7 to 5.5 v minimum instruction execution time 50 ns @20 mhz x1 input 2 to 10 mhz subclock 32.768 khz clock ring-osc ? cmos input 8 8 8 16 cmos i/o 43 59 76 112 port n-ch open-drain i/o 2 2 4 6 16-bit (tmp) 1 ch ? 1 ch ? 1 ch ? 1 ch 16-bit (tm0) 1 ch 2 ch 4 ch 6 ch 8-bit (tm5) 2 ch 2 ch 2 ch 2 ch 8-bit (tmh) 2 ch 2 ch 2 ch 2 ch interval timer 1 ch 1 ch 1 ch 1 ch watch 1 ch 1 ch 1 ch 1 ch wdt1 1 ch 1 ch 1 ch 1 ch timer wdt2 1 ch 1 ch 1 ch 1 ch rto 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch csi 2 ch 2 ch 2 ch 3 ch automatic transmit/receive 3-wire csi ? 1 ch 2 ch 2 ch uart 2 ch 2 ch 2 ch 3 ch uart supporting lin-bus ? ? ? ? serial interface i 2 c note 1 ch 1 ch 1 ch 2 ch address space ? 128 kb 3 mb 15 mb address bus ? 16 bits 22 bits 24 bits external bus mode ? multiplex only multiplex/separate dma controller ? ? ? ? 10-bit a/d converter 8 ch 8 ch 8 ch 16 ch 8-bit d/a converter ? ? 2 ch 2 ch external 8 8 8 8 interrupt internal 26 26 29 31 34 40 43 key return input 8 ch 8 ch 8 ch 8 ch reset pin provided poc none lvi none clock monitor none wdt1 provided reset wdt2 provided rom correction 4 regulator none provided standby function halt/idle/stop/sub-idle mode operating ambient temperature t a = ? 40 to +85 c note only in products with an i 2 c bus (y products). for the product name, refer to each user?s manual.
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 18 1.1.2 78k0/kx1+, 78k0/kx1 products lineup mask rom: 24 kb, ram: 768 b mask rom: 16 kb, ram: 768 b mask rom: 8 kb, ram: 512 b pd780101 78k0/kb1 30-pin ssop (7.62 mm 0.65 mm pitch) single-power flash: 24 kb, ram: 768 b single-power flash: 16 kb, ram: 768 b single-power flash: 8 kb, ram: 512 b pd780102 pd780103 pd78f0103 two-power flash: 24 kb, ram: 768 b 78k0/kb1+ pd78f0102h pd78f0103h pd78f0101h 44-pin lqfp (10 10 mm 0.8 mm pitch) pd78f0114 two-power flash: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb pd780114 mask rom: 24 kb, ram: 1 kb pd780113 mask rom: 16 kb, ram: 512 b pd780112 pd780111 78k0/kc1 single-power flash: 32 kb, ram: 1 kb single-power flash: 24 kb, ram: 1 kb single-power flash: 16 kb, ram: 512 b 78k0/kc1+ pd78f0113h pd78f0114h/hd note pd78f0112h mask rom: 8 kb, ram: 512 b pd78f0124 mask rom: 32 kb, ram: 1 kb pd780124 mask rom: 24 kb, ram: 1 kb pd780123 mask rom: 16 kb, ram: 512 b pd780122 mask rom: 8 kb, ram: 512 b pd780121 52-pin lqfp (10 10 mm 0.65 mm pitch) single-power flash: 32 kb, ram: 1 kb single-power flash: 24 kb, ram: 1 kb single-power flash: 16 kb, ram: 512 b 78k0/kd1+ pd78f0123h pd78f0124h/hd note pd78f0122h 78k0/kd1 two-power flash: 32 kb, ram: 1 kb pd78f0148 mask rom: 60 kb, ram: 2 kb pd780148 mask rom: 48 kb, ram: 2 kb pd780146 mask rom: 32 kb, ram: 1 kb pd780144 mask rom: 24 kb, ram: 1 kb pd780143 80-pin tqfp, qfp (12 12 mm 0.5 mm pitch, 14 14 mm 0.65 mm pitch) single-power flash: 60 kb, ram: 2 kb 78k0/kf1+ pd78f0148h/hd note 78k0/kf1 flash memory: 60 kb, ram: 2 kb pd78f0138 pd780138 pd780136 64-pin lqfp, tqfp (10 10 mm 0.5 mm pitch, 12 12 mm 0.65 mm pitch, 14 14 mm 0.8 mm pitch) 78k0/ke1+ pd78f0136h pd78f0138h/hd note 78k0/ke1 pd78f0134 mask rom: 32 kb, ram: 1 kb pd780134 mask rom: 24 kb, ram: 1 kb pd780133 mask rom: 16 kb, ram: 512 b pd780132 mask rom: 8 kb, ram: 512 b pd780131 single-power flash: 32 kb, ram: 1 kb single-power flash: 24 kb, ram: 1 kb single-power flash: 16 kb, ram: 512 b pd78f0133h pd78f0134h pd78f0132h flash memory: 32 kb, ram: 1 kb mask rom: 60 kb, ram: 2 kb mask rom: 48 kb, ram: 2 kb single-power flash: 60 kb, ram: 2 kb single-power flash: 48 kb, ram: 2 kb flash memory: 60 kb, ram: 2 kb
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 19 the function list of the 78k 0/kx1+ is shown below. product name item 78k0/kb1+ 78k0/kc1+ 78k0/kd 1+ 78k0/ke1+ 78k0/kf1+ number of pins 30 pins 44 pins 52 pins 64 pins 80 pins flash memory 8 k 16 k/24 k 16 k 24 k/32 k 16 k 24 k/32 k 16 k 24 k/ 32 k 48 k/ 60 k 60 k internal memory (byte) ram 512 768 512 1 k 512 1 k 512 1 k 2 k 2 k supply voltage v dd = 2.7 to 5.5 v minimum instruction execution time 0.125 s (16 mhz, when v dd = 4.0 to 5.5 v) 0.24 s (8.38 mhz, when v dd = 3.3 to 5.5 v) 0.4 s (5 mhz, when v dd = 2.7 to 5.5 v) x1 input 2 to 16 mhz rc 3 to 4 mhz (v dd = 2.7 to 5.5 v) ? sub ? 32.768 khz clock ring-osc 240 khz (typ.) cmos i/o 17 19 26 38 54 cmos input 4 8 cmos output 1 port n-ch open-drain i/o ? 4 16-bit (tm0) 1 ch 2 ch 8-bit (tm5) 2 ch 8-bit (tmh) 1 ch 2 ch watch ? 1 ch timer wdt 1 ch 3-wire csi note 1 ch 2 ch automatic transmit/ receive 3-wire csi ? 1 ch uart note ? 1 ch serial interface uart supporting lin-bus 1 ch 10-bit a/d converter 4 ch 8 ch external 6 7 8 9 9 interrupt internal 11 12 15 15 16 19 20 key return input ? 4 ch 8 ch reset pin provided poc 2.1 v 0.1 v (detection voltage fixed) lvi 2.35 v/2.6 v/2.85 v/3.1 v/3.3 v 0.15 v/3.5 v/3.7 v/3.9 v/4.1 v/4.3 v 0.2 v (selectable by software) clock monitor provided reset wdt provided clock output/buzzer output ? clock output only provided external bus interface ? provided multiplier/divider ? 16 bits 16 bits, 32 bits 16 bits rom correction ? provided ? self programming function provided on-chip debug function function provided only in pd78f0114hd, 78f0124hd, 78f 0138hd, and 78f0148hd standby function halt/stop mode operating ambient temperature ? 40 to +85 c note if the pin is an alternate-function pin, either function is selected for use.
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 20 the function list of the 78k0/kx1 is shown below. product name item 78k0/kb1 78k0/kc1 78k0/kd1 78k0/ke1 78k0/kf1 number of pins 30 pins 44 pi ns 52 pins 64 pins 80 pins mask rom 8 k 16 k/ 24 k ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 21 1.2 features { minimum instruction execution time: 50 ns (operation at main clock (f xx ) = 20 mhz) { general-purpose registers: 32 bits { cpu features: signed multiplication (16 { memory space: 64 mb of linear address space ? { interrupts and exceptions non-maskable interrupts: 3 sources maskable interrupts: 30 sources ( { i/o lines: total: 51 { key interrupt function { timer function 16-bit timer/event counter p: 1 channel 16-bit timer/event counter 0: 1 channel 8-bit timer/event counter 5: 2 channels 8-bit timer h: 2 channels 8-bit interval timer brg: 1 channel watch timer/interval timer: 1 channel watchdog timers watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel watchdog timer 2: 1 channel { serial interface asynchronous serial interface (uart): 2 channels 3-wire serial i/o (csi0): 2 channels i 2 c bus interface (i 2 c): 1 channel ( { a/d converter: 10-bit resolution { real-time output port: 6 bits { standby functions: halt/idle/stop modes, subclock/sub-idle modes { rom correction: 4 correction addresses specifiable { clock generator main clock oscillation (f x )/subclock oscillation (f xt ) cpu clock (f cpu ) 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { reset ? ? ?
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 22 { package: 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (fine pitch) (10 10) 1.3 applications { automotive ? system control of body electrical system (p ower windows, keyless entry reception, etc.) ? submicrocontroller of control system { home audio, car audio { av equipment { pc peripheral devices (keyboards, etc.) { household appliances ? outdoor units of air conditioners ? microwave ovens, rice cookers { industrial devices ? pumps ? vending machines ? fa 1.4 ordering information part number package quality grade pd703207gk- -9et pd703207gb- -8eu pd703207ygk- -9et pd703207ygb- -8eu pd70f3207hgk-9et pd70f3207hgb-8eu pd70f3207hygk-9et pd70f3207hygb-8eu 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (fine pitch) (10 10) 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (fine pitch) (10 10) 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (fine pitch) (10 10) 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (fine pitch) (10 10) standard standard standard standard standard standard standard standard remark indicates rom code suffix.
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 23 1.5 pin configuration (top view) 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (fine pitch) (10 10) pd703207gk- -9et pd703207gb- -8eu pd703207ygk- -9et pd703207ygb- -8eu pd70f3207hgk-9et pd70f3207hgb-8eu pd70f3207hygk-9et pd70f3207hygb-8eu
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pdl1 pdl0 pcm1/clkout pcm0 p915/intp6 p914/intp5 p913/intp4 p99/sck01 p98/so01 p97/si01 p96/ti51/to51 p91/rxd1/kr7 p90/txd1/kr6 p55/rtp05/kr5 p54/rtp04/kr4 ev dd p05/intp2 p06/intp3 p40/si00 p41/so00 p42/sck00 p30/txd0 p31/rxd0 p32/asck0 p33/tip00/top00 p34/tip01/top01 p35/ti010/to01 p50/ti011/rtp00/kr0 p51/ti50/rtp01/kr1 p52/to50/rtp02/kr2 p53/rtp03/kr3 ev ss p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p39/scl0 note 3 p38/sda0 note 3 pdl7 pdl6 pdl5/flmd1 note 1 pdl4 pdl3 pdl2 av ref0 av ss ic note 1 /flmd0 note 1 v dd nc note 2 v ss x1 x2 reset xt1 xt2 p00/toh0 p01/toh1 p02/nmi p03/intp0 p04/intp1 notes 1. ic pin: connect directly to v ss ( pd703207, 703207y). flmd0 pin: connect to v ss in normal operation mode ( pd70f3207h, 70f3207hy). flmd1 pin: used only in the pd70f3207h and 70f3207hy. 2. leave open. 3. the scl0 and sda0 pins can be used only in the pd703207y and 70f3207hy. caution make ev dd the same potential as v dd .
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 25 pin identification ani0 to ani7: analog input asck0: asynchronous serial clock av ref0 : analog reference voltage av ss : ground for analog clkout: clock output ev dd : power supply for port ev ss : ground for port flmd0, flmd1: flash programming mode ic: internally connected intp0 to intp6: external interrupt input kr0 to kr7: key return nc: non-connection nmi: non-maskable interrupt request p00 to p06: port 0 p30 to p35, p38, p39: port 3 p40 to p42: port 4 p50 to p55: port 5 p70 to p77: port 7 p90, p91, p96 to p99, p913 to p915: port 9 pcm0, pcm1: port cm pdl0 to pdl7: port dl reset: reset rtp00 to rtp05: real-time output port rxd0, rxd1: receive data sck00, sck01: serial clock scl0: serial clock sda0: serial data si00, si01: serial input so00, so01: serial output ti010, ti011, ti50, ti51, tip00, tip01: timer input to01, to50, to51, toh0, toh1, top00, top01: timer output txd0, txd1: transmit data v dd : power supply v ss : ground x1, x2: crystal for main clock xt1, xt2: crystal for subclock
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 26 1.6 function block configuration (1) internal block diagram nmi to01 ti010, ti011 so00, so01 si00, si01 sck00, sck01 intp0 to intp6 intc 16-bit timer/event counter 0: 1 ch top00, top01 tip00, tip01 16-bit timer/ event counter p: 1 ch to50, to51 ti50, ti51 8-bit timer/event counter 5: 2 ch toh0, toh1 txd0, txd1 rxd0, rxd1 asck0 rtp00 to rtp05 kr0 to kr7 uart : 2 ch rto: 1 ch sda0 note 1 scl0 note 1 i 2 c note 1 : 1 ch watchdog timer: 2 ch key interrupt function watch timer 128 kb 4 kb ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu port a/d converter pdl0 to pdl7 pcm0, pcm1 p70 to p77 p50 to p55 p40 to p42 p30 to p35, p38, p39 p00 to p06 av ref0 av ss ani0 to ani7 v dd ic note 2 /flmd0 note 2 flmd1 note 2 ev dd ev ss v ss instruction queue bcu csi0: 2 ch 8-bit timer h: 2 ch rom correction cg pll clkout x1 x2 xt1 xt2 reset p90, p91, p96 to p99, p913 to p915 notes 1. only in the pd703207y, 70f3207hy 2. ic: pd703207, 703207y flmd0, flmd1: pd70f3207h, 70f3207hy
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 27 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 28 (i) watchdog timer two watchdog timer channels are provided on chip to detect program loops and system abnormalities. watchdog timer 1 can be used as an interval timer. when used as a watchdog timer, it generates a non- maskable interrupt request signal (intwdt1) or system reset signal (wdtres1) after an overflow occurs. when used as an interval timer, it generates a mask able interrupt request signal (intwdtm1) after an overflow occurs. watchdog timer 2 operates by default following reset release. it generates a non-maskable interrupt request signal (intwdt2) or system rese t signal (wdtres2) after an overflow occurs. (j) serial interface (sio) the v850es/ke1 includes three kinds of serial interf aces: an asynchronous serial interface (uartn), a clocked serial interface (csi0n), and an i 2 c bus interface (i 2 c0). the
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 29 (o) ports as shown below, the following ports have general-p urpose port functions and control pin functions. port i/o alternate function p0 7-bit i/o nmi, external interrupt, timer output p3 8-bit i/o serial interface, timer i/o p4 3-bit i/o serial interface p5 6-bit i/o timer i/o, key interrupt function, real-time output function p7 8-bit input a/d converter analog input p9 9-bit i/o serial interface, timer i/o, external interrupt, key interrupt function pcm 2-bit i/o clock output pdl 8-bit i/o ?
chapter 1 introduction preliminary user?s manual u16892ej1v0ud 30 1.7 overview of functions part number pd703207, 703207y pd70f3207h, 70f3207hy rom 128 kb 128 kb (flash memory) internal memory high-speed ram 4 kb memory space 64 mb general-purpose registers 32 bits 32 registers ceramic/crystal/external clock when pll not used 2 to 8 mhz (the value may change after evaluation): 2.7 to 5.5 v main clock (oscillation frequency) when pll used 2 to 5 mhz: 4.5 to 5.5 v, 2 mhz: 2.7 to 5.5 v subclock (oscillation frequency) crystal/external clock (32.768 khz) minimum instruction execution time 50 ns (when main clock operated at (f xx ) = 20 mhz) dsp function 32 32 = 64: 200 to 250 ns (at 20 mhz) 32 32 + 32 = 32: 300 ns (at 20 mhz) 16 16 = 32: 50 to 100 ns (at 20 mhz) 16 16 + 32 = 32: 150 ns (at 20 mhz) i/o ports 51 ? input: 8 ? i/o: 43 (among these, n-ch open-drain output se lectable: 4, fixed to n-ch open-drain output: 2) timer 16-bit timer/event counter p: 1 channel 16-bit timer/event counter 0: 1 channel 8-bit timer/event counter 5: 2 channels (16-bit timer/event counter: usable as 1 channel) 8-bit timer h: 2 channels watch timer: 1 channel 8-bit interval timer: 1 channel watchdog timer: 2 channels real-time output port 4 bits 1, 2 bits 1, or 6 bits 1 a/d converter 10-bit resolution 8 channels serial interface csi: 2 channels uart: 2 channels i 2 c bus: 1 channel note 1 dedicated baud rate generator: 2 channels interrupt sources external: 9 (9) note 2 , internal: 25/26 note 1 power save function stop/idle/halt operating supply voltage 4.5 to 5.5 v (a t 20 mhz)/2.7 to 5.5 v (at 8 mhz) package 64-pin plastic tqfp (12 12 mm) 64-pin plastic lqfp (fine pitch) (10 10 mm) notes 1. only in the pd703207y, 70f3207hy 2. the figure in parentheses indica tes the number of external inte rrupts for which stop mode can be released.
preliminary user?s manual u16892ej1v0ud 31 chapter 2 pin functions the names and functions of the pins of the v850es/ke1 are described below, divided into port pins and non-port pins. the pin i/o buffer power supplies ar e divided into two systems; av ref0 and ev dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 ev dd reset, ports 0, 3 to 5, 9, cm, dl 2.1 list of pin functions (1) port pins (1/2) pin name pin no. i/o pull-up resistor function alternate function p00 12 toh0 p01 13 toh1 p02 14 nmi p03 15 intp0 p04 16 intp1 p05 17 intp2 p06 18 i/o yes port 0 i/o port input/output can be specified in 1-bit units. intp3 p30 22 txd0 p31 23 rxd0 p32 24 asck0 p33 25 tip00/top00 p34 26 tip01/top01 p35 27 yes ti010/to01 p38 55 sda0 note 2 p39 56 i/o no note 1 port 3 i/o port input/output can be specified in 1-bit units. p38 and p39 are fixed to n-ch open-drain output. scl0 note 2 p40 19 si00 p41 20 so00 p42 21 i/o yes port 4 i/o port input/output can be specified in 1-bit units. p41 and p42 can be specified as n-ch open- drain output in 1-bit units. sck00 notes 1. an on-chip pull-up resistor can be provided by a mask option (only in the
chapter 2 pin functions preliminary user?s manual u16892ej1v0ud 32 (2/2) pin name pin no. i/o pull-up resistor function alternate function p50 28 ti011/rtp00/kr0 p51 29 ti50/rtp01/kr1 p52 30 to50/rtp02/kr2 p53 31 rtp03/kr3 p54 34 rtp04/kr4 p55 35 i/o yes port 5 i/o port input/output can be specified in 1-bit units. rtp05/kr5 p70 64 ani0 p71 63 ani1 p72 62 ani2 p73 61 ani3 p74 60 ani4 p75 59 ani5 p76 58 ani6 p77 57 input no port 7 input port ani7 p90 36 txd1/kr6 p91 37 rxd1/kr7 p96 38 ti51/to51 p97 39 si01 p98 40 so01 p99 41 sck01 p913 42 intp4 p914 43 intp5 p915 44 i/o yes port 9 i/o port input/output can be specified in 1-bit units. p98 and p99 can be specified as n-ch open- drain output in 1-bit units. intp6 pcm0 45 ? pcm1 46 i/o no port cm i/o port input/output can be specified in 1-bit units. clkout pdl0 47 ? pdl1 48 ? pdl2 49 ? pdl3 50 ? pdl4 51 ? pdl5 52 flmd1 note pdl6 53 ? pdl7 54 i/o no port dl i/o port input/output can be specified in 1-bit units. ? note only in the pd70f3207h, 70f3207hy
chapter 2 pin functions preliminary user?s manual u16892ej1v0ud 33 (2) non-port pins (1/2) pin name pin no. i/o pull-up resistor function alternate function ani0 64 p70 ani1 63 p71 ani2 62 p72 ani3 61 p73 ani4 60 p74 ani5 59 p75 ani6 58 p76 ani7 57 input no analog voltage input for a/d converter p77 asck0 24 input yes uart0 serial clock input p32 av ref0 1 ? ? reference voltage for a/d converter and positive power supply for alternate-function ports ? av ss 2 ? ? ground potential for a/d converter ? clkout 46 output no internal system clock output pcm1 ev dd 33 ? ? positive power supply for external ? ev ss 32 ? ? ground potential for external ? flmd0 note 1 3 ? flmd1 note 1 52 ? ? flash programming mode setting pin pdl5 ic note 2 8 ? ? internally connected ? intp0 15 p03 intp1 16 p04 intp2 17 p05 intp3 18 p06 intp4 42 p913 intp5 43 p914 intp6 44 input yes external interrupt request input (maskable, analog noise elimination) p915 kr0 28 p50/ti011/rtp00 kr1 29 p51/ti50/rtp01 kr2 30 p52/to50/rtp02 kr3 31 p53/rtp03 kr4 34 p54/rtp04 kr5 35 p55/rtp05 kr6 36 p90/txd1 kr7 37 input yes key return input p91/rxd1 nc 5 ? ? not internally connected. leave open. ? nmi 14 input yes external interrupt input (non-maskable, analog noise elimination) p02 reset 9 input ? system reset input ? notes 1. only in the
chapter 2 pin functions preliminary user?s manual u16892ej1v0ud 34 (2/2) pin name pin no. i/o pull-up resistor function alternate function rtp00 28 p50/ti011/kr0 rtp01 29 p51/ti50/kr1 rtp02 30 p52/to50/kr2 rtp03 31 p53/kr3 rtp04 34 p54/kr4 rtp05 35 output yes real-time output port p55/kr5 rxd0 23 serial receive data input for uart0 p31 rxd1 37 input yes serial receive data input for uart1 p91/kr7 sck00 21 p42 sck01 41 i/o yes serial clock i/o for csi00 and csi01 n-ch open-drain output can be specified in 1- bit units. p99 scl0 note 1 56 i/o no note 2 serial clock i/o for i 2 c0 fixed to n-ch open-drain output p39 sda0 note 1 55 i/o no note 2 serial transmit/receive data i/o for i 2 c0 fixed to n-ch open-drain output p38 si00 19 serial receive data input for csi00 p40 si01 39 input yes serial receive data input for csi01 p97 so00 20 p41 so01 40 output yes serial transmit data output for csi00 and csi01 n-ch open-drain output can be specified in 1-bit units. p98 ti010 27 capture trigger input/external event input for tm01 p35/to01 ti011 28 capture trigger input for tm01 p50/rtp00/kr0 ti50 29 external event input for tm50 p51/rtp01/kr1 ti51 38 external event input for tm51 p96/to51 tip00 25 capture trigger input/external event input/external clo ck input for tmp0 p33/top00 tip01 26 input yes capture trigger input p34/top01 to01 27 timer output for tm01 p35/ti010 to50 30 timer output for tm50 p52/rtp02/kr2 to51 38 timer output for tm51 p96/ti51 toh0 12 timer output for tmh0 p00 toh1 13 timer output for tmh1 p01 top00 25 p33/tip00 top01 26 output yes timer output for tmp0 p34/tip01 txd0 22 serial transmit data output for uart0 p30 txd1 36 output yes serial transmit data output for uart1 p90/kr6 v dd 4 ? ? positive power s upply pin for internal ? v ss 6 ? ? ground potential for internal ? x1 7 input no ? x2 8 ? no connecting resonator for main clock ? xt1 10 input no ? xt2 11 ? no connecting resonator for subclock ? notes 1. only in the pd703207y, 70f3207hy 2. an on-chip pull-up resistor can be provided by a mask option (only in the pd703207, 703207y).
chapter 2 pin functions preliminary user?s manual u16892ej1v0ud 35 2.2 pin i/o circuits and recommend ed connection of unused pins (1/2) pin alternate function pin no. i/o circuit type recommended connection p00 toh0 12 p01 toh1 13 5-a p02 nmi 14 p03 to p06 intp0 to intp3 15 to 18 5-w p30 txd0 22 5-a p31 rxd0 23 p32 asck0 24 p33 tip00/top00 25 p34 tip01/top01 26 p35 ti010/to01 27 5-w p38 sda0 note 1 55 p39 scl0 note 1 56 13-ae p40 si00 19 5-w p41 so00 20 10-e p42 sck00 21 10-f p50 ti011/rtp00/kr0 28 p51 ti50/rtp01/kr1 29 p52 to50/rtp02/kr2 30 p53 rtp03/kr3 31 8-a p54 rtp04/kr4 34 p55 rtp05/kr5 35 10-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. p70 to p77 ani0 to ani7 64 to 57 9-c connect to av ref0 or av ss . p90 txd1/kr6 36 p91 rxd1/kr7 37 p96 ti51/to51 38 8-a p97 si01 39 5-w p98 so01 40 10-e p99 sck01 41 10-f p913 to p915 intp4 to intp6 42 to 44 5-w pcm0 ? 45 pcm1 clkout 46 pdl0 to pdl4 ? 47 to 51 pdl5 flmd1 note 2 52 pdl6, pdl7 ? 53, 54 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. av ref0 ? 1 ? directly connect to v dd . av ss ? 2 ? ? notes 1. only in the pd703207y, 70f3207hy 2. only in the pd70f3207h, 70f3207hy
chapter 2 pin functions preliminary user?s manual u16892ej1v0ud 36 (2/2) pin alternate function pin no. i/o circuit type recommended connection ev dd ? 33 ? ? ev ss ? 32 ? ? flmd0 note 1 ? 3 ? connect to v ss in normal operation mode. ic note 2 ? 3 ? directly connect to ev ss or v ss or pull down with a 10 k ? resistor. nc ? 5 ? leave open. reset ? 9 2 ? v dd ? 4 ? ? v ss ? 6 ? ? x1 ? 7 ? ? x2 ? 8 ? ? xt1 ? 10 16 directly connect to v ss note 3 . xt2 ? 11 16 leave open. notes 1. only in the pd70f3207h, 70f3207hy 2. only in the pd703207, 703207y 3. be sure to set the psmr.xtstp bit to 1 when this pin is not used.
chapter 2 pin functions preliminary user?s manual u16892ej1v0ud 37 2.3 pin i/o circuits (1/2) type 2 type 8-a type 5 type 9-c type 5-a type 10-a type 5-w type 10-e schmitt-triggered input with hysteresis characteristics in data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable p-ch v dd pull-up enable in comparator + ? av ref0 (threshold voltage) p-ch n-ch input enable pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch data output disable v dd p-ch in/out n-ch open drain pull-up enable v dd p-ch data output disable v dd p-ch in/out n-ch open drain input enable pull-up enable v dd p-ch v ss av ss v ss v ss v ss v ss v ss
chapter 2 pin functions preliminary user?s manual u16892ej1v0ud 38 (2/2) type 10-f type 13-ae type 16 p-ch feedback cut-off xt1 xt2 data output disable v dd p-ch in/out n-ch open drain input enable pull-up enable v dd p-ch data output disable input enable in/out n -ch v ss mask option v dd v ss remark read v dd as ev dd . also, read v ss as ev ss .
preliminary user?s manual u16892ej1v0ud 39 chapter 3 cpu functions the cpu of the v850es/ke1 is based on th e risc architecture and executes mo st instructions in one clock cycle by using 5-stage pipeline control. 3.1 features { number of instructions: 83 { minimum instruction execution time: 50.0 ns (@ 20 mhz operation: 4.5 to 5.5 v) 125 ns note (@ 8 mhz operation: 2.7 to 5.5 v) { memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear { general-purpose registers: 32 bits { internal 32-bit architecture { 5-stage pipeline control { multiply/divide instructions { saturated operation instructions { 32-bit shift instruction: 1 clock { load/store instruction with long/short format { four types of bit manipulation instructions ? ? ? ?
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 40 3.2 cpu register set the cpu registers of the v850es/ke1 can be classified in to two categories: a general-purpose program register set and a dedicated system register set. all the registers have 32-bit width. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register)
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 41 3.2.1 program register set the program register set includes general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. all of these registers c an be used as a data variable or address variable. however, r0 and r30 are implicitly us ed by instructions and care must be ex ercised when using these registers. r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer when performing memory access with the sld and sst instructions. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. t herefore, before using these registers, their contents mu st be saved so that they are not lost, and they must be restor ed to the registers after the registers have been used. there are cases when r2 is used by the real-time os. if r2 is not used by the real-time os, r2 can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved regist er working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os to be used) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (area for placing program code) r6 to r29 address/data variable register r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution (2) program counter (pc) this register holds the address of the in struction under execution. the lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occu rs from bit 25 to bit 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address under execution 0 after reset 00000000h
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 42 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. read from and write to system regist ers are performed by setting the system register numbers shown below with the system register load/st ore instructions (ldsr, stsr instructions). table 3-2. system register numbers operand specification enabled system register no. system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 yes yes 1 interrupt status saving register (eipsw) note 1 yes yes 2 nmi status saving register (fepc) note 1 yes yes 3 nmi status saving register (fepsw) note 1 yes yes 4 interrupt source register (ecr) no yes 5 program status word (psw) yes yes 6 to 15 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no 16 callt execution status saving register (ctpc) yes yes 17 callt execution status saving register (ctpsw) yes yes 18 exception/debug trap status saving register (dbpc) yes note 2 yes 19 exception/debug trap status saving register (dbpsw) yes note 2 yes 20 callt base pointer (ctbp) yes yes 21 to 31 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no notes 1. since only one set of these registers is available, the contents of this register must be saved by the program when multiple interrupt servicing is enabled. 2. can be accessed only during the period from the dbtrap instruction to the dbret instruction. caution even if bit 0 of eipc, fepc, or ctpc is set (1) by the ldsr instruction, bit 0 is ignored during return with the reti instruction following interrupt servicing (because bit 0 of pc is fixed to 0). when setting a value to eipc, fepc, and ctpc, set an even number (bit 0 = 0).
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 43 (1) interrupt status saving registers (eipc, eipsw) there are two interrupt status sa ving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (pc) are saved to eipc and the contents of the program status word (psw) are saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), t he contents are saved to the nmi status saving registers (fepc, fepsw)). the address of the next instruction fo llowing the instruction executed when a software exception or maskable interrupt occurs is saved to eipc, e xcept for some instructions (refer to 17.9 periods in which interrupts are not acknowledged by cpu ). the current psw contents are saved to eipsw. since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved (fixed to 0) for future function expansion. when the reti instruction is execut ed, the values in eipc and eipsw are restored to the pc and psw, respectively. 31 0 eipc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 44 (2) nmi status saving registers (fepc, fepsw) there are two nmi status saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), the contents of the program co unter (pc) are saved to fepc and the contents of the program status word (psw) are saved to fepsw. the address of the next instruction fo llowing the instruction executed when a non-maskable interrupt occurs is saved to fepc, except fo r some instructions. the current psw contents are saved to fepsw. since there is only one set of nmi stat us saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is performed. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served (fixed to 0) for future function expansion. 31 0 fepc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (3) interrupt source register (ecr) upon occurrence of an interrupt or an exception, the inte rrupt source register (ecr) holds the source of an interrupt or an exception. the value held by ecr is the exception code c oded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 45 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the program status (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruct ion, the new contents become valid immediately following completion of ldsr instruction execution. interrupt request acknowledgment is held pending while a write to the psw is being executed by the ldsr instruction. bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servici ng is in progress. this flag is set to 1 when an nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in prog ress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt r equest acknowledgment is enabled. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do no t become saturated. this flag is neither set nor cleared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow occu rred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2 ov note indicates whether overflow o ccurred during an operation. 0: no overflow occurred 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0. remark note is explained on the following page.
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 46 (2/2) note during saturated operation, the saturated operation results are det ermined by the contents of the ov flag and s flag. the sat flag is set (to 1) only when the ov flag is set (to 1) during saturated operation. flag status operation result status sat ov s saturated operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation 0 1 actual operation result (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execut ion status saving registers, ctpc and ctpsw. when the callt instruction is execut ed, the contents of the program count er (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instructi on after the callt instruction. the current psw contents are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are re served (fixed to 0) for future function expansion. 31 0 ctpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 47 (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/de bug trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, the contents of the program counter (pc) are saved to dbpc, and the program status word (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instructi on after the instruction executed when an exception trap or debug trap occurs. the current psw contents are saved to dbpsw. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are re served (fixed to 0) for future function expansion. 31 0 dbpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 0 ctbp (base address) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 48 3.3 operating modes the v850es/ke1 has the foll owing operating modes. (1) normal operating mode after the system has been released from the reset state, execution branches to the reset entry address of the internal rom, and instructi on processing is started. (2) flash memory programming mode this mode is valid only in flash memory versions ( pd70f3207h and 70f3207hy). when this mode is specified, the internal flash me mory can be programmed by using a flash programmer. (a) specifying operating mode the operating mode is specified acco rding to the status (input leve l) of the flmd0 and flmd1 pins. in the normal operating mode, input a low level to the flmd0 pin during the reset period. a high level is input to the flmd0 pin by the flash programmer in the flash memory programming mode if a flash programmer is connected. in the self-programming mode, input a high level to this pin from an external circuit. fix the specification of these pins in the application system and do not change the setting of these pins during operation. flmd0 flmd1 operating mode l normal operating mode h l flash memory programming mode h h setting prohibited remark h: high level l: low level : don?t care
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 49 3.4 address space 3.4.1 cpu address space in a linear address space (program space) of up to 64 mb, up to 1 mb of internal rom area and internal ram area are supported for instruction address addressing. during operand addressing (data access), up to 4 gb of linear address space (data space) is supported. however, the 4 gb address space is viewed as 64 images of a 64 mb physical address space. in other words, the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. address space image program space internal ram area access-prohibited area access-prohibited area internal rom area data space image 63 image 1 image 0 on-chip peripheral i/o area internal ram area access-prohibited area internal rom area 1 mb 4 gb 64 mb ? ? ?
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 50 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the program counter (p c), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calc ulation, the higher 6 bits ignore this and remain 0. therefore, the lower-limit address of the program space, 0000 0000h, and the upper-limit address, 03ffffffh, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution no instructions can be fetched from the 4 kb area of 03fff000h to 03ffffffh because this area is an on-chip peripheral i/o area. the refore, do not execute any branch operation instructions in which the destination addres s will reside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit addre ss of the data space, address 0000 0000h, and the upper-limit address, ffffffffh, are contiguous addresses, and the data space is wrapped around at t he boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction (?) direction
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 51 3.4.3 memory map the v850es/ke1 has reserved areas as shown below. figure 3-2. data memory map (physical addresses) 3ffffffh 3fec000h 3febfffh 0100000h 00fffffh 0000000h 3fff000h 3ffefffh 3fff000h 3ffefffh 3ffffffh 3fec000h (80 kb) access-prohibited area internal ram area (60 kb) on-chip peripheral i/o area (4 kb) access-prohibited area internal rom area (1 mb)
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 52 figure 3-3. program memory map 03ff0000h 03feffffh 03fff000h 03ffefffh 03ffffffh 00100000h 000fffffh 00000000h internal ram area (60 kb) access-prohibited area (program fetch disabled area) access-prohibited area (program fetch disabled area) internal rom area (1 mb)
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 53 3.4.4 areas (1) internal rom area an area of 1 mb from 0000000h to 00fffffh is reserved for the internal rom area. a 128 kb area from 0000000h to 001ffffh is provided in the v850es/ke1. addresses 0020000h to 00fffffh are an access-prohibited area. figure 3-4. internal rom area (128 kb) 00fffffh 0020000h 001ffffh 0000000h access-prohibited area internal rom area (128 kb) (2) internal ram area an area of 60 kb maximum from 3ff0000h to 3ffef ffh is reserved for the internal ram area. a 4 kb area from 3ffe000h to 3ffefffh is provided as physical internal ram in the v850es/ke1. addresses 3ff0000h to 3ffdfffh are an access-prohibited area. figure 3-5. internal ram area (4 kb) internal ram area (4 kb) access-prohibited area 3ffefffh 3ffe000h 3ffdfffh 3ff0000h fffefffh fffe000h fffdfffh fff0000h physical address space logical address space
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 54 (3) on-chip peripheral i/o area a 4 kb area from 3fff000h to 3ffffffh is rese rved as the on-chip peripheral i/o area. figure 3-6. on-chip peripheral i/o area 3ffffffh 3fff000h on-chip peripheral i/o area (4 kb) fffffffh ffff000h physical address space logical address space peripheral i/o registers assigned with functions such as on-chip peripheral i/o operation mode specification and state monitoring are mapped to the on-chip peripheral i/o area. program fetches are not allowed in this area. cautions 1. if word access of a register is atte mpted, halfword access to th e word area is performed twice, first for the lower bits , then for the higher bits, ignoring the lower 2 address bits. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the access is a read operation. if a write access is performed, only the data in the lower 8 bits is written to the register. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed.
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 55 3.4.5 recommended use of address space the architecture of the v850es/ke1 r equires that a register that serves as a pointer be secured for address generation when operand data in t he data space is accessed. the address stored in this pointer
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 56 figure 3-7. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom use prohibited use prohibited internal ram on-chip peripheral i/o note program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffe000h 03ffdfffh 03ff0000h 03feffffh 00020000h 0001ffffh 00100000h 000fffffh 00000000h xfffffffh xffff000h xfffefffh xfffe000h xfffdfffh xfff0000h xffeffffh x0100000h x00fffffh x0000000h note access to this area is prohibited. to access the on-chip peripheral i/o in th is area, specify addresses ffff000h to fffffffh. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd703207 and 703207y.
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 57 3.4.6 peripheral i/o registers (1/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff004h port dl register pdl r/w 00h note 1 fffff00ch port cm register pcm r/w 00h note 1 fffff024h port dl mode register pmdl r/w ffh fffff02ch port cm mode register pmcm r/w ffh fffff04ch port cm mode control register pmccm r/w 00h fffff06eh system wait control register vswc r/w 77h fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ffh fffff101h interrupt mask register 0h imr0h r/w ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ffh fffff103h interrupt mask register 1h imr1h r/w ffh fffff106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ffh fffff110h interrupt control register wdt1ic r/w 47h fffff112h interrupt control register pic0 r/w 47h fffff114h interrupt control register pic1 r/w 47h fffff116h interrupt control register pic2 r/w 47h fffff118h interrupt control register pic3 r/w 47h fffff11ah interrupt control register pic4 r/w 47h fffff11ch interrupt control register pic5 r/w 47h fffff11eh interrupt control register pic6 r/w 47h fffff124h interrupt control register tm0ic10 r/w 47h fffff126h interrupt control register tm0ic11 r/w 47h fffff128h interrupt control register tm5ic0 r/w 47h fffff12ah interrupt control register tm5ic1 r/w 47h fffff12ch interrupt control register csi0ic0 r/w 47h fffff12eh interrupt control register csi0ic1 r/w 47h fffff130h interrupt control register sreic0 r/w 47h fffff132h interrupt control register sric0 r/w 47h fffff134h interrupt control register stic0 r/w 47h fffff136h interrupt control register sreic1 r/w 47h fffff138h interrupt control register sric1 r/w 47h fffff13ah interrupt control register stic1 r/w 47h fffff13ch interrupt control register tmhic0 r/w 47h fffff13eh interrupt control register tmhic1 r/w 47h fffff142h interrupt control register iicic0 note 2 r/w 47h fffff144h interrupt control register adic r/w 47h fffff146h interrupt control register kric r/w 47h notes 1. the output latch is 00h. when input, the pin status is read. 2. only in the pd703207y, 70f3207hy
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 58 (2/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff148h interrupt control register wtiic r/w
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 59 (3/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff452h port 9 mode control register pmc9 r/w
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 60 (4/6) operable bit unit address function register name symbol r/w 1 8 16 32 after reset fffff617h prescaler mode register 01 prm01 r/w
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 61 (5/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffa13h asynchronous serial interf ace status register 1 asis1 r 00h fffffa14h transmit buffer register 1 txb1 r/w ffh fffffa15h asynchronous serial interface transmit status register 1 asif1 r 00h fffffa16h clock select register 1 cksr1 r/w 00h fffffa17h baud rate generator control register 1 brgc1 r/w ffh fffffb00h tip00 noise elimination control register p0nfc r/w 00h fffffb04h tip01 noise elimination control register p1nfc r/w 00h fffffc00h external interrupt falling edge specification register 0 intf0 r/w 00h fffffc13h external interrupt falling edge specification register 9h intf9h r/w 00h fffffc20h external interrupt rising edge specification register 0 intr0 r/w 00h fffffc33h external interrupt rising edge specification register 9h intr9h r/w 00h fffffc40h pull-up resistor option register 0 pu0 r/w 00h fffffc46h pull-up resistor option register 3 pu3 r/w 00h fffffc48h pull-up resistor option register 4 pu4 r/w 00h fffffc4ah pull-up resistor option register 5 pu5 r/w 00h fffffc52h pull-up resistor option register 9 pu9 r/w 0000h fffffc52h pull-up resistor option register 9l pu9l r/w 00h fffffc53h pull-up resistor option register 9h pu9h r/w 00h fffffc67h port 3 function register h pf3h r/w 00h fffffc68h port 4 function register pf4 r/w 00h fffffc73h port 9 function register h pf9h r/w 00h fffffd00h clocked serial interf ace mode register 00 csim00 r/w 00h fffffd01h clocked serial interface clock selection register 0 csic0 r/w 00h fffffd02h clocked serial interface re ceive buffer register 0 sirb0 r 0000h fffffd02h clocked serial interface receive buffer register 0l sirb0l r 00h fffffd04h clocked serial interface tran smit buffer register 0 sotb0 r/w 0000h fffffd04h clocked serial interface tr ansmit buffer register 0l sotb0l r/w 00h fffffd06h clocked serial interface read-onl y receive buffer register 0 sirbe0 r 0000h fffffd06h clocked serial interface read- only receive buffer register 0l sirbe0l r 00h fffffd08h clocked serial interface initial transmit buffer register 0 sotbf0 r/w 0000h fffffd08h clocked serial interface initia l transmit buffer register 0l sotbf0l r/w 00h fffffd0ah serial i/o shift register 0 sio00 r/w 00h fffffd0ah serial i/o shift register 0l sio00l r/w 0000h fffffd10h clocked serial interf ace mode register 01 csim01 r/w 00h fffffd11h clocked serial interface clock selection register 1 csic1 r/w 00h fffffd12h clocked serial interface re ceive buffer register 1 sirb1 r 0000h fffffd12h clocked serial interface receive buffer register 1l sirb1l r 00h fffffd14h clocked serial interface tran smit buffer register 1 sotb1 r/w 0000h fffffd14h clocked serial interface tr ansmit buffer register 1l sotb1l r/w 00h fffffd16h clocked serial interface read-onl y receive buffer register 1 sirbe1 r 0000h fffffd16h clocked serial interface read- only receive buffer register 1l sirbe1l r 00h
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 62 (6/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffd18h clocked serial interface initial transmit buffer register 1 sotbf1 r/w 0000h fffffd18h clocked serial interface initia l transmit buffer register 1l sotbf1l r/w 00h fffffd1ah serial i/o shift register 1 sio01 r/w 00h fffffd1ah serial i/o shift register 1l sio01l r/w 0000h fffffd80h iic shift register 0 iic0 note r/w 00h fffffd82h iic control register 0 iicc0 note r/w 00h fffffd83h slave address register 0 sva0 note r/w 00h fffffd84h iic clock selection register 0 iiccl0 note r/w 00h fffffd85h iic function expansion register 0 iicx0 note r/w 00h fffffd86h iic status register 0 iics0 note r 00h fffffd8ah iic flag register 0 iicf0 note r/w 00h note only in the pd703207y, 70f3207hy
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 63 3.4.7 special registers special registers are registers that prevent invalid da ta from being written when an inadvertent program loop occurs. the v850es/ke1 has the following three special registers. ? ? ? ? ? st.b r11, psmr[r0] ; psmr register setting (idle, stop mode setting) <1> mov 0x02, r10 <2> st.b r10, prcmd[r0] ; prcmd register write <3> st.b r10, psc[r0] ; psc register setting <4> nop note ; dummy instruction <5> nop note ; dummy instruction <6> nop note ; dummy instruction <7> nop note ; dummy instruction <8> nop note ; dummy instruction (next instruction) no special sequence is required to read special registers. note when switching to the idle mode or the stop m ode (psc.stp bit = 1), 5 nop instructions must be inserted immediately after switching is performed. cautions 1. interrupts are not acknowledged for the store instruction for the prcmd register. this is because continuous execution of store instructi ons by the program in steps <2> and <3> above is assumed. if another instruction is placed between step <2> and <3>, the above sequence may not be realized when an interrupt is acknowle dged for that instruction, which may cause malfunction. 2. the data written to the prcmd register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <3>) when writing to the prcmd register (step <2>). the same applies to when using a general- purpose register for addressing.
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 64 (2) command register (prcmd) the prcmd register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs. only the first write operat ion to the special register following the execution of a previously executed writ e operation to the prcmd register, is valid. as a result, register values can be overwritten onl y using a preset sequence, preventing invalid write operations. this register can only be written in 8-bit units (if it is read, an undefined value is returned). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 65 (3) system status register (sys) this register is allocated with status flags showing the operat ing state of the entire system. this register can be read or writt en in 8-bit or 1-bit units. 0 protection error has not occurred protection error has occurred prerr 0 1 detection of protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the operation conditions of the prerr flag are described below. (a) set conditions (prerr = 1) (i) when a write operation to the s pecial register takes place without write operation being performed to the prcmd register (when step <3> is performed without performing step <2> as described in 3.4.7 (1) setting data to special registers ). (ii) when a write operation (including bit manipulation instruction) to an on-chip peripheral i/o register other than a special register is performed follo wing write to the prcmd register (when <3> in 3.4.7 (1) setting data to special registers is not a special register). remark regarding the special registers other than the wdtm register (pcc and psc registers), even if on-chip peripheral i/o register read (except bit ma nipulation instruction) (internal ram access, etc.) is performed in between wr ite to the prcmd register and wr ite to a special register, the prerr flag is not set and setting data can be written to the special register. (b) clear conditions (prerr = 0) (i) when 0 is written to the prerr flag (ii) when system reset is performed cautions 1. if 0 is written to the prerr bit of the sys register that is not a special register immediately following write to the prcmd re gister, the prerr bi t becomes 0 (write priority). 2. if data is written to the prcmd register that is not a special register immediately following write to the prcmd regist er, the prerr bit becomes 1.
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 66 3.4.8 cautions (1) wait when accessing register be sure to set the following register before using the v850es/ke1. ? system wait control register (vswc) after setting the vswc register, set t he other registers as required. when using an external bus, set the vswc register and then set the various pins to the control mode by setting the port-related registers. (a) system wait control register (vswc) the vswc register controls the bus access wait ti me for the on-chip perip heral i/o registers. access to the on-chip peripheral i/o register lasts 3 cl ocks (during no wait), but in the v850es/ke1, waits are required according to the internal system clo ck frequency. set the values shown below to the vswc register according to the internal system clock frequency that is used. this register can be read or written in 8-bit units (address: fffff06eh, after reset: 77h). operation conditions internal system clock frequency (f clk ) vswc register setting 32 khz f clk < 16.6 mhz 00h v dd = 5 v 10% (f x = 2 to 5 mhz) 16.6 mhz f clk 20 mhz 01h v dd = 4.0 to 5.5 v 32 khz f clk 16 mhz 00h v dd = 2.7 to 4.0 v 32 khz f clk 8 mhz 00h remark f x : main clock oscillation frequency (b) access to special on-chip peripheral i/o register this product has two types of internal system buses. one type is for the cpu bus and the ot her is for the peripheral bus to interface with low-speed peripheral hardware. since the cpu bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access between the cpu and peripheral hardware, illegal data may be passed unexpectedly. therefore, when accessing peripheral hardware that may cause a conf lict, the number of access cycles is changed so that the data is received/passed correctly in the cpu. as a result, the cpu does not shift to the next instruction processing and enters t he wait status. when this wait stat us occurs, the number of execution clocks of the instruction is increased by the number of wait clocks. note this with caution when performing real-time processing. when accessing a special on-chip peripheral i/o regist er, additional waits may be required further to the waits set by the vswc register. the access conditions at that time and the method to calculate the number of waits to be inserted (number of cpu clocks) are shown below.
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 67 peripheral function register name access k wdtm1 write 1 to 5 watchdog timer 1 (wdt1) {(1/f x )
chapter 3 cpu functions preliminary user?s manual u16892ej1v0ud 68 (2) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the dec ode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of t he instruction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mo v instruction immediately before the sld instruction and an interrupt request conflict before exec ution of the ld instruction is complete, the executi on result of instruction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 (b) countermeasure when executing the sld instruction immediately afte r instruction , avoid the above operation using either of the following methods. ? insert a nop instruction immediat ely before the sld instruction. ? do not use the same register as the sld instructi on destination register in the above instruction executed immediately befor e the sld instruction. ? ? ?
preliminary user?s manual u16892ej1v0ud 69 chapter 4 port functions 4.1 features { input-only ports: 8 pins { i/o ports: 43 pins ? fixed to n-ch open-drain output: 2 ? switchable to n-ch open-drain output: 4 { input/output can be specified in 1-bit units 4.2 basic port configuration the v850es/ke1 incorporates a total of 51 i/o port pins consis ting of ports 0, 3 to 5, 7, 9, cm, and dl (including 8 input-only port pins). the port configuration is shown below. p00 p06 port 0 p90 p91 p96 p99 p913 p915 port 9 pcm0 pcm1 port cm pdl0 pdl7 port dl p30 p35 p38 p39 port 3 p40 p42 port 4 p50 p55 port 5 p70 p77 port 7 table 4-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 ev dd reset, ports 0, 3 to 5, 9, cm, dl
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 70 4.3 port configuration table 4-2. port configuration item configuration control registers port n register (pn: n = 0, 3 to 5, 7, 9, cm, dl) port n mode register (pmn: n = 0, 3 to 5, 9, cm, dl) port n mode control register (pmcn: n = 0, 3 to 5, 9, cm) port n function control register (pfcn: n = 3, 5, 9) port 3 function control expansion register (pfce3) port n function register (pfn: n = 3, 4, 9) pull-up resistor option register (pun: n = 0, 3 to 5, 9) ports input only: 8 i/o: 43 pull-up resistors software control: 31 (1) port n register (pn) data i/o with external devices is performed by writing to and reading from the pn regist er. the pn register is configured of a port latch that re tains the output data and a circ uit that reads the pin status. each bit of the pn register corresponds to one pin of port n and can be read or written in 1-bit units. pn7 0 is output 1 is output pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h note (output latch) r/w note input-only port pins are undefined. writing to and reading from the pn register is executed as follows independent of the se tting of the pmcn register. table 4-3. reading to/writing from pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm bit = 0) write to the output latch note . in the port mode (pmcnm bit = 0), the contents of the output latch are output from the pin. the value of the output latch is read. input mode (pmnm bit = 1) write to the output latch. the status of the pin is not affected note . the pin status is read. note the value written to the output latch is retained until a value is next written to the output latch.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 71 (2) port n mode register (pmn) pmn specifies the input m ode/output mode of the port. each bit of the pmn register corresponds to one pin of port n and can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of i/o mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) pmcn specifies the port mode/alternate function. each bit of the pmcn register corresponds to one pin of port n and can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w (4) port n function control register (pfcn) pfcn is a register that specifies the alternate function to be us ed when one pin has two or more alternate functions. each bit of the pfcn register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 72 (5) port n function control expansion register (pfcen) pfcen is a register that specifies t he alternate function to be used when one pin has three or more alternate functions. each bit of the pfcen register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 (6) port n function register (pfn) pfn is a register that specifies normal output/n-ch open-drain output. each bit of the pfn register corresponds to one pin of port n and can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit is valid only when the pmn.pmnm bit is 0 (output mode) regardl ess of the setting of the pmcn register. when the pmnm bit is 1 (input mode) , the set value in the pfn register is invalid. example <1> when the value of t he pfn register is valid pfnm bit = 1 ? n-ch open-drain output is specified. pmnm bit = 0 ? output mode is specified. pmcnm bit = 0 or 1 <2> when the value of the pfn register is invalid pfnm bit = 0 ? n-ch open-drain output is specified. pmnm bit = 1 ? input mode is specified. pmcnm bit = 0 or 1
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 73 (7) pull-up resistor option register (pun) pun is a register that specifies the c onnection of an on-chip pull-up resistor. each bit of the pun register corresponds to one pin of port n and can be specified in 1-bit units. pun7 pun6 pun5 pun4 pun3 pun2 pun1 pun0 pun after reset: 00h r/w not connected connected punm 0 1 control of on-chip pull-up resistor connection
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 74 (8) port settings set the ports as follows. figure 4-1. register settings and pin functions pmcn register output mode input mode pmn register ? 0 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark switch to the alternate functi on using the following procedure. <1> set the pfcn and pfcen registers. <2> set the pmcn register. <3> set the intrn or intfn register (t o specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 75 4.3.1 port 0 port 0 is a 7-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 0 includes the following alternate functions. table 4-4. alternate-function pins of port 0 pin name pin no. alternate function i/o pull note remark block type p00 12 toh0 output d-2 p01 13 toh1 output ? d-2 p02 14 nmi input h-1 p03 15 intp0 input h-1 p04 16 intp1 input h-1 p05 17 intp2 input h-1 p06 18 intp3 input yes analog noise elimination h-1 note software pull-up function caution p02 to p06 have hysteresis characteristics when the alternate f unction is input, but not in the port mode. (1) port 0 register (p0) 0 0 is output 1 is output p0n 0 1 control of output data (in output mode) (n = 0 to 6) p0 p06 p05 p04 p03 p02 p01 p00 after reset: 00h (output latch) r/w address: fffff400h (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 control of i/o mode (n = 0 to 6) pm0 pm06 pm05 pm04 pm03 pm02 pm01 pm00 after reset: ffh r/w address: fffff420h
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 76 (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode i/o port toh1 output pmc01 0 1 specification of p01 pin operation mode i/o port toh0 output pmc00 0 1 specification of p00 pin operation mode after reset: 00h r/w address: fffff440h (4) pull-up resistor option register 0 (pu0) 0 not connected connected pu0n 0 1 control of on-chip pull-up resistor connection (n = 0 to 6) pu0 pu06 pu05 pu04 pu03 pu02 pu01 pu00 after reset: 00h r/w address: fffffc40h
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 77 4.3.2 port 3 port 3 is an 8-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port 3 includes the following alternate functions. table 4-5. alternate-function pins of port 3 pin name pin no. alternate function i/o pull note 1 remark block type p30 22 txd0 output d-2 p31 23 rxd0 input d-1-1 p32 24 asck0 input d-1-2 p33 25 tip00/top00 i/o g-7-3 p34 26 tip01/top01 i/o g-7-3 p35 27 ti010/to01 i/o yes ? e-6 p38 55 sda0 note 3 i/o k p39 56 scl0 note 3 i/o no note 2 n-ch open-drain output k notes 1. software pull-up function 2. an on-chip pull-up resistor can be provided by a mask option (only in the mask rom versions). 3. only in the
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 78 (1) port 3 register (p3) 0 is output 1 is output p3n 0 1 control of output data (in output mode) (n = 0 to 5, 8, 9) p3 (p3h note ) after reset: 00h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h 0 0 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 p39 p38 8 9 10 11 12 13 14 15 (p3l) note when reading from or writing to bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p3h register. remark the p3 register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the p3 register are used as the p3h register and as the p3l register, re spectively, this register can be read or written in 8-bit or 1-bit units. (2) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 control of i/o mode (n = 0 to 5, 8, 9) 1 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 1 pm3 (pm3h note ) 1 1 1 1 1 pm39 pm38 8 9 10 11 12 13 14 15 (pm3l) note when reading from or writing to bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm3h register. remark the pm3 register can be read or written in 16-bit units. when the higher 8 bits and the lower 8 bits of the pm3 register are used as the pm3h register and as the pm3l register, respective ly, this register can be read or written in 8-bit or 1-bit units.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 79 (3) port 3 mode control register (pmc3) pmc3 (pmc3h note 1 ) i/o port scl0 i/o pmc39 0 1 specification of p39 pin operation mode i/o port sda0 i/o pmc38 0 1 specification of p38 pin operation mode i/o port ti010 input/to01 output pmc35 0 1 specification of p35 pin operation mode i/o port tip01 input/top01 output pmc34 0 1 specification of p34 pin operation mode i/o port tip00 input/top00 output pmc33 0 1 specification of p33 pin operation mode i/o port asck0 input pmc32 0 1 specification of p32 pin operation mode i/o port rxd0 input pmc31 0 1 specification of p31 pin operation mode i/o port txd0 output pmc30 0 1 specification of p30 pin operation mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 00 00 00 pmc39 note 2 pmc38 note 2 8 9 10 11 12 13 14 15 (pmc3l) notes 1. when reading from or writing to bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc3h register. 2. valid only in the
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 80 (4) port 3 function register h (pf3h) 0 when used as normal port (n-ch open-drain output) when used as alternate-function (n-ch open-drain output) pf3n 0 1 specification of normal port/alternate function (n = 8, 9) pf3h 0 0 0 0 0 pf39 pf38 after reset: 00h r/w address: fffffc67h caution when using p38 and p39 as n-ch open-drai n-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p3n bit = 1
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 81 (7) pull-up resistor option register 3 (pu3) 0 not connected connected pu3n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) pu3 0 pu35 pu34 pu33 pu32 pu31 pu30 after reset: 00h r/w address: fffffc46h caution an on-chip pull-up r esistor can be provided for p38 and p39 by a mask option (only in the pd703207, 703207y). (8) specifying alternate-function pins of port 3 caution when the p3n pin is speci fied as an alternate function by the pmc3n bit with the pfc3n and pfce3n bits maintaining the initial value (0 ), output becomes undefined. therefore, to specify the p3n pin as an altern ate function, set the pfc3n and pfce3n bits first and then set the pmc3n bit to 1 (n = 3, 4). pfc35 specification of alter nate-function pin of p35 pin 0 ti010 input 1 to01 output pfce34 pfc34 specification of alte rnate-function pin of p34 pin 0 0 setting prohibited 0 1 setting prohibited 1 0 tip01 input 1 1 top01 output pfce33 pfc33 specification of alte rnate-function pin of p33 pin 0 0 setting prohibited 0 1 setting prohibited 1 0 tip00 input 1 1 top00 output
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 82 4.3.3 port 4 port 4 is a 3-bit i/o port for which i/o se ttings can be controll ed in 1-bit units. port 4 includes the following alternate functions. table 4-6. alternate-function pins of port 4 pin name pin no. alternate function i/o pull note remark block type p40 19 si00 input ? d-1-2 p41 20 so00 output f-1 p42 21 sck00 i/o yes n-ch open-drain output can be selected. f-2 note software pull-up function caution p40 and p42 have hysteresis characteristics when th e alternate function is input, but not in the port mode. (1) port 4 register (p4) 0 0 is output 1 is output p4n 0 1 control of output data (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 control of i/o mode (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 83 (3) port 4 mode control register (pmc4) 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sck00 i/o pmc42 0 1 specification of p42 pin operation mode i/o port so00 output pmc41 0 1 specification of p41 pin operation mode i/o port si00 input pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h (4) port 4 function register (pf4) 0 normal output n-ch open-drain output pf4n 0 1 control of normal output/n-ch open-drain output (n = 1, 2) pf4 0 0 0 0 pf42 pf41 0 after reset: 00h r/w address: fffffc68h caution when using p41 and p42 as n-ch open- drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p4n bit = 1
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 84 4.3.4 port 5 port 5 is a 6-bit i/o port for which i/o se ttings can be controll ed in 1-bit units. port 5 includes the following alternate functions. table 4-7. alternate-function pins of port 5 pin name pin no. alternate function i/o pull note remark block type p50 28 ti011/rtp00/kr0 i/o e-5 p51 29 ti50/rtp01/kr1 i/o e-5 p52 30 to50/rtp02/kr2 i/o e-4 p53 31 rtp03/kr3 i/o e-9 p54 34 rtp04/kr4 i/o e-9 p55 35 rtp05/kr5 i/o yes ? e-9 note software pull-up function (1) port 5 register (p5) 0 is output 1 is output p5n 0 1 control of output data (in output mode) (n = 0 to 5) p5 after reset: 00h (output latch) r/w address: fffff40ah 0 0 p55 p54 p53 p52 p51 p50 (2) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 control of i/o mode (n = 0 to 5) 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah pm5
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 85 (3) port 5 mode control register (pmc5) i/o port/kr5 input rtp05 output pmc55 0 1 specification of p55 pin operation mode i/o port/kr4 input rtp04 output pmc54 0 1 specification of p54 pin operation mode 0 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 after reset: 00h r/w address: fffff44ah pmc5 i/o port/kr3 input rtp03 output pmc53 0 1 specification of p53 pin operation mode i/o port/kr2 input to50 output/rtp02 output pmc52 0 1 specification of p52 pin operation mode i/o port/kr1 input ti50 input/rtp01 output pmc51 0 1 specification of p51 pin operation mode i/o port/kr0 input ti011 input/rtp00 output pmc50 0 1 specification of p50 pin operation mode
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 86 (4) port 5 function control register (pfc5) caution when the p5n pin is sp ecified as an alternate function by the pmc5.pmc5n bit with the pfc5n bit maintaining the initial value (0), out put becomes undefined. therefore, to specify the p5n pin as alternate function 2, set the pfc5 n bit to 1 first and then set the pmc5n bit to 1 (n = 3 to 5). pfc5 rtp05 output pfc55 1 specification of alternate-function pin of p55 pin rtp03 output pfc53 1 specification of alternate-function pin of p53 pin rtp04 output pfc54 1 specification of alternate-function pin of p54 pin after reset: 00h r/w address: fffff46ah 0 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 to50 output rtp02 output pfc52 0 1 specification of alternate-function pin of p52 pin ti50 input rtp01 output pfc51 0 1 specification of alternate-function pin of p51 pin ti011 input rtp00 output pfc50 0 1 specification of alternate-function pin of p50 pin (5) pull-up resistor option register 5 (pu5) 0 not connected connected pu5n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) 0 pu55 pu54 pu53 pu52 pu51 pu50 after reset: 00h r/w address: fffffc4ah pu5
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 87 4.3.5 port 7 port 7 is an 8-bit input-only port for which all the pins are fixed to input. port 7 includes the following alternate functions. table 4-8. alternate-function pins of port 7 pin name pin no. alternate function i/o pull note remark block type p70 64 ani0 input a-1 p71 63 ani1 input a-1 p72 62 ani2 input a-1 p73 61 ani3 input a-1 p74 60 ani4 input a-1 p75 59 ani5 input a-1 p76 58 ani6 input a-1 p77 57 ani7 input no ? a-1 note software pull-up function (1) port 7 register (p7) input low level input high level p7n 0 1 input data read (n = 0 to 7) after reset: undefined r address: fffff40eh p77 p76 p75 p74 p73 p72 p71 p70 p7
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 88 4.3.6 port 9 port 9 is a 9-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 9 includes the following alternate functions. table 4-9. alternate-function pins of port 9 pin name pin no. alternate function i/o pull note remark block type p90 36 txd1/kr6 i/o e-9 p91 37 rxd1/kr7 i/o e-7 p96 38 ti51/to51 i/o e-9 p97 39 si01 i/o ? e-8 p98 40 so01 output g-9 p99 41 sck01 i/o n-ch open-drain output can be specified. g-8 p913 42 intp4 i/o h-3 p914 43 intp5 i/o h-3 p915 44 intp6 i/o no analog noise elimination h-3 note software pull-up function caution p97, p99, and p913 to p915 have hysteresis characteristics when the alternate function is input, but not in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 89 (1) port 9 register (p9) 0 is output 1 is output p9n 0 1 control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15) after reset: 00h (output latch) r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p915 p9 (p9h note ) p914 p913 0 0 0 p99 p98 p97 p96 0 0 0 0 p91 p90 8 9 10 11 12 13 14 15 (p9l) note when reading from or writing to bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p9h register. remark the p9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lower 8 bits of the p9 register are used as the p9h register and as the p9l register, re spectively, these registers can be read or written in 8-bit or 1-bit units. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 control of i/o mode (n = 0, 1, 6 to 9, 13 to 15) pm96 1 1 1 1 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm9 (pm9h note ) pm914 pm913 1 1 1 pm99 pm98 8 9 10 11 12 13 14 15 (pm9l) note when reading from or writing to bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. remark the pm9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pm9 register are used as the pm9h register and as the pm9l register, re spectively, this register can be read or written in 8-bit or 1-bit units. (3) port 9 mode control register (pmc9)
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 90 i/o port intp6 input pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 0 0 0 0 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc9 (pmc9h note ) pmc914 pmc913 0 0 0 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port intp5 input pmc914 0 1 specification of p914 pin operation mode i/o port sck01 i/o pmc99 0 1 specification of p99 pin operation mode i/o port intp4 input pmc913 0 1 specification of p913 pin operation mode i/o port so01 output pmc98 0 1 specification of p98 pin operation mode (pmc9l) i/o port si01 input pmc97 0 1 specification of p97 pin operation mode i/o port/ti51 input to51 output pmc96 0 1 specification of p96 pin operation mode i/o port/kr7 input rxd1 input pmc91 0 1 specification of p91 pin operation mode i/o port/kr6 input txd1 output pmc90 0 1 specification of p90 pin operation mode note when reading from or writing to bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. remark the pmc9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pmc9 register are used as the pmc9h register and as the pmc9l r egister, respectively, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 91 (4) port 9 function register h (pf9h) 0 normal output n-ch open-drain output pf9n 0 1 control of normal output/n-ch open-drain output (n = 0, 1) pf9h 0 0 0 0 0 pf99 pf98 after reset: 00h r/w address: fffffc73h caution when using p98 and p99 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 be fore setting the pin to n-ch open-drain output. p9n bit = 1
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 92 (5) port 9 function control register (pfc9) caution when the p9n pin is sp ecified as an alternate function by the pmc9.pmc9n bit with the pfc9.pfc9n bit maintaining the initial value (0 ), output becomes undefined. therefore, to specify the p9n pin as alternate function 2, set the pfc9n bit to 1 first and then set the pmc9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15). pfc9 (pfc9h note ) intp6 input pfc915 1 specification of p915 pin operation mode in control mode intp5 input pfc914 1 specification of p914 pin operation mode in control mode intp4 input pfc913 1 specification of p913 pin operation mode in control mode after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 0 0 0 0 pfc91 pfc90 pfc915 pfc914 pfc913 0 0 0 pfc99 pfc98 8 9 10 11 12 13 14 15 sck01 i/o pfc99 1 specification of p99 pin operation mode in control mode so01 output pfc98 1 specification of p98 pin operation mode in control mode (pfc9l) si01 input pfc97 1 specification of p97 pin operation mode in control mode to51 output pfc96 1 specification of p96 pin operation mode in control mode rxd1 input pfc91 1 specification of p91 pin operation mode in control mode txd1 output pfc90 1 specification of p90 pin operation mode in control mode note when reading from or writing to bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. remark the pfc9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pfc9 register are used as the pfc9h register and as t he pfc9l register, respective ly, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 93 (6) pull-up resistor option register 9 (pu9) not connected connected pu9n 0 1 control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15) pu9 (pu9h note ) after reset: 0000h r/w address: pu9 fffffc52h, pu9l fffffc52h, pu9h fffffc53h pu97 pu96 0 0 0 0 pu91 pu90 pu915 pu914 pu913 0 0 0 pu99 pu98 8 9 10 11 12 13 14 15 (pu9l) note when reading from or writing to bits 8 to 15 of the pu9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu9h register. remark the pu9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pu9 register are used as the pu9h register and as the pu9l register, respectively, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 94 4.3.7 port cm port cm is a 2-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port cm includes the following alternate functions. table 4-10. alternate-function pins of port cm pin name pin no. alternate function i/o pull note remark block type pcm0 45 ? ? b-1 pcm1 46 clkout output no ? c-2 note software pull-up function (1) port cm register (pcm) 0 is output 1 is output pcmn 0 1 control of output data (in output mode) (n = 0, 1) after reset: 00h (output latch) r/w address: fffff00ch 0 pcm 0 0 0 0 0 pcm1 pcm0 (2) port cm mode register (pmcm) output mode input mode pmcmn 0 1 control of i/o mode (n = 0, 1) after reset: ffh r/w address: fffff02ch 1 pmcm 1 1 1 1 1 pmcm1 pmcm0 (3) port cm mode control register (pmccm) 0 pmccm 0 0 0 0 0 pmccm1 0 i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode after reset: 00h r/w address: fffff04ch
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 95 4.3.8 port dl port dl is an 8-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port dl includes the following alternate functions. table 4-11. alternate-function pins of port dl pin name pin no. alternate function i/o pull note remark block type pdl0 47 ? ? b-1 pdl1 48 ? ? b-1 pdl2 49 ? ? b-1 pdl3 50 ? ? b-1 pdl4 51 ? ? b-1 pdl5 52 ? ? b-1 pdl6 53 ? ? b-1 pdl7 54 ? ? no ? b-1 note software pull-up function (1) port dl register (pdl) 0 is output 1 is output pdln 0 1 control of output data (in output mode) (n = 0 to 7) after reset: 00h (output latch) r/w address: fffff004h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdl (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 control of i/o mode (n = 0 to 7) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: fffff024h pmdl
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 96 4.4 block diagrams figure 4-2. block diagram of type a-1 internal bus rd a/d input signal pmn p-ch n-ch
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 97 figure 4-3. block diagram of type b-1 wr pm rd address wr port pmn pmmn output latch (pmn) internal bus selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 98 figure 4-4. block diagram of type c-2 wr pmc rd address output signal of alternate-function 1 wr port pmn pmcmn wr pm pmmn output latch (pmn) internal bus selector selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 99 figure 4-5. block diagram of type d-1-1 wr pmc rd address note input signal of alternate-function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch output latch (pmn) internal bus selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 100 figure 4-6. block diagram of type d-1-2 wr pmc rd address note input signal of alternate-function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch output latch (pmn) internal bus selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 101 figure 4-7. block diagram of type d-2 wr pmc rd address output signal of alternate-function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch output latch (pmn) internal bus selector selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 102 figure 4-8. block diagram of type e-4 wr pmc rd address alternate-function input signal in port mode output signal of alternate-function 2 output signal of alternate-function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 103 figure 4-9. block diagram of type e-5 wr pmc rd address alternate-function input signal in port mode input signal of alternate-function 1 output signal of alternate-function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 104 figure 4-10. block diagram of type e-6 wr pmc rd address input signal of alternate-function 1 output signal of alternate-function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector note note there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 105 figure 4-11. block diagram of type e-7 wr pmc rd address alternate-function input signal in port mode input signal of alternate-function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 106 figure 4-12. block diagram of type e-8 wr pmc rd address note input signal of alternate-function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 107 figure 4-13. block diagram of type e-9 wr pmc rd address alternate-function input signal in port mode output signal of alternate-function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 108 figure 4-14. block diagram of type f-1 wr pmc rd address wr port pmn pmcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) output signal of alternate-function 1 internal bus selector selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 109 figure 4-15. block diagram of type f-2 wr pmc rd address output signal of alternate-function 1 input signal of alternate-function 1 output enable signal of alternate-function 1 output enable signal of alternate-function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss note p-ch n-ch output latch (pmn) internal bus selector selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 110 figure 4-16. block diagram of type g-7-3 p-ch wr pmc rd address note input signal of alternate-function 3 output signal of alternate-function 4 wr port pmn pmcmn wr pfce pfcemn wr pm pmmn wr pfc pfcmn wr pu pumn ev dd output latch (pmn) internal bus selector selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 111 figure 4-17. block diagram of type g-8 wr pmc rd address output enable signal of alternate-function 2 input signal of alternate-function 2 output signal of alternate-function 2 wr port pmn note pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) output enable signal of alternate-function 2 internal bus selector selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 112 figure 4-18. block diagram of type g-9 wr pmc rd address output signal of alternate-function 2 wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) internal bus selector selector selector
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 113 figure 4-19. block diagram of type h-1 wr pmc rd address input signal of alternate-function 1 wr port pmn note 2 pmcmn wr intf intfmn note 1 wr pu pumn wr pm pmmn detection of noise elimination edge wr intr intrmn note 1 ev dd p-ch output latch (pmn) internal bus selector selector notes 1. refer to 17.4 external interrupt request input pins (nmi, intp0 to intp6 ). 2. there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 114 figure 4-20. block diagram of type h-3 wr pmc rd address wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr intf intfmn note 1 wr intr intrmn note 1 ev dd p-ch input signal of alternate-function 2 note 2 detection of noise elimination edge output latch (pmn) internal bus selector selector notes 1. refer to 17.4 external interrupt request input pins (nmi, intp0 to intp6) . 2. there are no hysteresis characteristics in the port mode.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 115 figure 4-21. block diagram of type k wr pmc rd address output signal of alternate-function 1 input signal of alternate-function 1 wr port pmcmn wr pf pfmn wr pm pmmn pmn ev dd ev ss note mask option n-ch output latch (pmn) internal bus selector selector selector note there are no hysteresis characteristics in the port mode. 4.5 port register setting when alternate function is used table 4-12 shows the port register settings when each port is used for an alternate function. when using a port pin as an alternate-functi on pin, refer to description of each pin.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 116 table 4-12. settings when port pins are used for alternate functions (1/3) other bits (registers) ? ? ? ? ? ? ? ? ? ? pfce33 (pfce3) = 1 pfce33 (pfce3) = 1 pfce34 (pfce3) = 1 pfce34 (pfce3) = 1 ? ? pf38 (pf3) = 1 pf39 (pf3) = 1 pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? pfc33 = 0 pfc33 = 1 pfc34 = 0 pfc34 = 1 pfc35 = 0 pfc35 = 1 ? ? pmcnx bit of pmcn register pmc00 = 1 pmc01 = 1 pmc02 = 1 pmc03 = 1 pmc04 = 1 pmc05 = 1 pmc06 = 1 pmc30 = 1 pmc31 = 1 pmc32 = 1 pmc33 = 1 pmc33 = 1 pmc34 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pmc38 = 1 pmc39 = 1 pmnx bit of pmn register pm00 = setting not required pm01 = setting not required pm02 = setting not required pm03 = setting not required pm04 = setting not required pm05 = setting not required pm06 = setting not required pm30 = setting not required pm31 = setting not required pm32 = setting not required pm33 = setting not required pm33 = setting not required pm34 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required pm38 = setting not required pm39 = setting not required pnx bit of pn register p00 = setting not required p01 = setting not required p02 = setting not required p03 = setting not required p04 = setting not required p05 = setting not required p06 = setting not required p30 = setting not required p31 = setting not required p32 = setting not required p33 = setting not required p33 = setting not required p34 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required p38 = 1 p39 = 1 i/o output output input input input input input output input input input output input output input output i/o i/o alternate function intp0 intp1 intp2 intp3 txd0 rxd0 asck0 tip00 top00 tip01 top01 ti010 to01 sda0 note scl0 note pin name p00 p01 p02 p03 p04 p05 p06 p30 p31 p32 p33 p34 p35 p38 p39 function name ? pf41 (pf4) = don?t care pf42 (pf4) = don?t care ? ? ? pmc40 = 1 pmc41 = 1 pmc42 = 1 pm40 = setting not required pm41 = setting not required pm42 = setting not required p40 = setting not required p41 = setting not required p42 = setting not required input output i/o si00 so00 sck00 p40 p41 p42 toh0 toh1 nmi note only in the pd703207y, 70f3207hy
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 117 table 4-12. settings when port pins are used for alternate functions (2/3) other bits (registers) ? ? krm0 (krm) = 1 ? ? krm1 (krm) = 1 ? ? krm2 (krm) = 1 ? krm3 (krm) = 1 krm4 (krm) = 1 krm5 (krm) = 1 pfcnx bit of pfcn register pfc50 = 0 pfc50 = 1 pfc50 = 0 pfc51 = 0 pfc51 = 1 pfc51 = 0 pfc52 = 0 pfc52 = 1 pfc52 = 0 pfc53 = 1 pfc53 = 0 pfc54 = 1 pfc54 = 0 pfc55 = 1 pfc55 = 0 pmcnx bit of pmcn register pmc50 = 1 pmc50 = 1 pmc50 = 0 pmc51 = 1 pmc51 = 1 pmc51 = 0 pmc52 = 1 pmc52 = 1 pmc52 = 0 pmc53 = 1 pmc53 = 0 pmc54 = 1 pmc54 = 0 pmc55 = 1 pmc55 = 0 pmnx bit of pmn register pm50 = setting not required pm50 = setting not required pm50 = 1 pm51 = setting not required pm51 = setting not required pm51 = 1 pm52 = setting not required pm52 = setting not required pm52 = 1 pm53 = setting not required pm53 = 1 pm54 = setting not required pm54 = 1 pm55 = setting not required pm55 = 1 pnx bit of pn register p50 = setting not required p50 = setting not required p50 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p53 = setting not required p53 = setting not required p54 = setting not required p54 = setting not required p55 = setting not required p55 = setting not required i/o input output input input output input output output input output input output input output input alternate function function name ti011 rtp00 kr0 ti50 rtp01 kr1 to50 rtp02 kr2 rtp03 kr3 rtp04 kr4 rtp05 kr5 pin name p50 p51 p52 p53 p54 p55 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required input input input input input input input input ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 p70 p71 p72 p73 p74 p75 p76 p77 ? ?
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 118 table 4-12. settings when port pins are used for alternate functions (3/3) other bits (registers) ? krm6 (krm) = 1 ? krm7 (krm) = 1 ? ? ? pf98 (pf9) = don?t care pf98 (pf9) = don?t care pfcnx bit of pfcn register pfc90 = 1 pfc90 = 0 pfc91 = 1 pfc91 = 0 pfc96 = 0 pfc96 = 1 pfc97 = 1 pfc98 = 1 pfc99 = 1 pmcnx bit of pmc90 = 1 pmc90 = 0 pmc91 = 1 pmc91 = 0 pmc96 = 0 pmc96 = 1 pmc97 = 1 pmc98 = 1 pmc99 = 1 pmnx bit of pmn register pm90 = setting not required pm90 = 1 pm91 = setting not required pm91 = 1 pm96 = 1 pm96 = setting not required pm97 = setting not required pm98 = setting not required pm99 = setting not required pnx bit of pn register p90 = setting not required p90 = setting not required p91 = setting not required p91 = setting not required p96 = setting not required p96 = setting not required p97 = setting not required p98 = setting not required p99 = setting not required i/o output input input input input output input output i/o alternate function function name txd1 kr6 rxd1 kr7 ti51 to51 si01 so01 sck01 pin name p90 p91 p96 p97 p98 p99 ? pfc913 = 1 pmc913 = 1 pm913 = setting not required p913 = setting not required input intp4 p913 ? pfc914 = 1 pmc914 = 1 pm914 = setting not required p914 = setting not required input intp5 p914 ? pfc915 = 1 pmc915 = 1 pm915 = setting not required p915 = setting not required input intp6 p915 ? ? pmccm1 = 1 pmcm1 = setting not required pcm1 = setting not required output clkout pcm1 pmcn register
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 119 4.6 cautions 4.6.1 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. when pdl0 is an output port, pdl1 to pdl7 are input ports (all pin statuses are high level), and the value of the port latch is 00h, if the output of output port pdl0 is changed from low level to high level via a bit manipulation instruction, the value of the port latch is ffh. explanation: the targets of writ ing to and reading from the pn regi ster of a port whose pmnm bit is 1 are the output latch and pin status, respectively. a bit manipulation instruction is executed in the following order in the v850es/ke1. <1> the pn register is read in 8-bit units. <2> the targeted one bit is manipulated. <3> the pn register is written in 8-bit units. in step <1>, the value of the out put latch (0) of pdl0, which is an output port, is read, while the pin statuses of pdl1 to pdl7, which ar e input ports, are read. if the pin statuses of pdl1 to pdl7 are high level at this time, the read value is feh. the value is changed to ffh by the manipulation in <2>. ffh is written to the output la tch by the manipulation in <3>. figure 4-22. bit manipula tion instruction (pdl0) low-level output bit manipulation instruction (set1 0, pdl[r0]) is executed for pdl0 bit. pin status: high level pdl0 pdl1 to pdl7 port dl latch 00000000 low-level output pin status: high level pdl0 pdl1 to pdl7 port dl latch 11111111 bit manipulation instruction for pdl0 bit <1> the pdl register is read in 8-bit units. ? in the case of pdl0, an output port, the value of the port latch (0) is read. ? in the case of pdl1 to pdl7, input ports, the pin status (1) is read. <2> set pdl0 bit to 1. <3> write the results of <2> to the output latch of the pdl register in 8-bit units.
chapter 4 port functions preliminary user?s manual u16892ej1v0ud 120 4.6.2 hysteresis characteristics in port mode, the following ports do not have hysteresis characteristics. p02 to p06 p31 to p35, p38, p39 p40, p42 p97, p99, p913 to p915
preliminary user?s manual u16892ej1v0ud 121 chapter 5 clock generation function 5.1 overview the following clock generation functions are available. { main clock oscillator (these values may change after evaluation) ? f x = 2 mhz (f xx = 8 mhz, v dd = 2.7 to 5.5 v, in pll mode) ? f x = 2 to 5 mhz (f xx = 8 to 20 mhz, v dd = 4.5 to 5.5 v, in pll mode) ? f x = 2 to 8 mhz (f xx = 2 to 8 mhz, v dd = 2.7 to 5.5 v, in clock-through mode) { subclock oscillator ? 32.768 khz { multiplication ( 4) function by pll (phase locked loop) ? clock-through mode/pll mode selectable ? usable voltage: v dd = 2.7 to 5.5 v { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output function remark f x : main clock oscillation frequency f xx : main clock frequency
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 122 5.2 configuration figure 5-1. clock generator frc bit mck bit ck2 to ck0 bits selpll bit pllon bit cls bit, ck3 bit stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock watch timer clock, watchdog timer 2 clock peripheral clock, watchdog timer 2 clock watchdog timer 1 clock internal system clock interval timer brg main clock oscillator main clock oscillator stop control xt1 xt2 clkout x1 x2 idle mode idle control idle mode selector pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1024 f brg = f x /2 to f x /2 12 f xt f xt f xx f x f xw idle control idle mode selector selector mfrc bit f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f brg : watch timer clock frequency f xw : watchdog timer 1 clock frequency
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 123 (1) main clock oscillator the main clock oscillator oscillates the following frequencies (f x ) (these values may change after evaluation). f x = 2 mhz (v dd = 2.7 to 5.5 v, in pll mode) f x = 2 to 5 mhz (v dd = 4.5 to 5.5 v, in pll mode) f x = 2 to 8 mhz (v dd = 2.7 to 5.5 v, in clock-through mode) (2) subclock oscillator the subclock oscillator oscillat es a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscill ator is stopped in the st op mode or when the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) prescaler 1 this prescaler generates the clock (f xx to f xx /1024) to be supplied to the following on-chip peripheral functions: tmp0, tm01, tm50, tm51, tmh0, tmh1, csi00, csi01, uart0, uart1, i 2 c0, adc, and wdt2 (5) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom correction, rom, and ram blocks, and can be output from the clkout pin. (6) interval timer brg this circuit divides the clock (f x ) generated by the main clock oscillator to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, refer to chapter 10 interval timer, watch timer . (7) pll this circuit multiplies the clock (f x ) generated by the main clock oscillator. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be sele cted by using the pllctl.selpll bit. operation of the pll c an be started or stopped by the pllctl.pllon bit.
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 124 5.3 register (1) processor clock control register (pcc) the pcc register is a special register. data can be wr itten to this register only in combination of specific sequences (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. after reset, pcc is set to 03h. (1/2) frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 control of main clock oscillator used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. < > < > < > note the cls bit is a read-only bit.
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 125 (2/2) f xx f xx /2 f xx /4 f xx /8 (default value) f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 126 (a) example of setting main clock operation _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 127 (b) example of setting subclock operation _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time _wait_ost : nop nop nop addi -1, r11, r11 mp r0, r11 bne _program_wait <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts bnz _check_cls remark the above description is an exampl e. note with caution that t he cls bit is read in a closed loop in <4>.
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 128 5.4 operation 5.4.1 operation of each clock the following table shows the oper ation status of each clock. table 5-1. operation status of each clock pcc register cls bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) { { { { { { { { { { { { { { cpu clock (f cpu ) { { { { { { { { { { { { { { { { { { { { { wdt1 clock (f xw ) { { { { { { { { { { { { { { { { remark o: operable
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 129 5.5 pll function 5.5.1 overview the pll function is used to output the operating clock of the cpu and per ipheral macro at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. when pll function is used: input clock = 2 to 5 mhz (f xx : 8 to 20 mhz) clock-through mode: input clock = 2 to 10 mhz (f xx : 2 to 10 mhz) (these values may change after evaluation) 5.5.2 register (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the security function of pll and rto. this register can be read or written in 8-bit or 1-bit units. after reset, pllctl is set to 01h. 0 pllctl 0 0 0 0 rtost0 note selpll pllon pll stopped pll operating pllon 0 1 pll operation stop register clock-through operation pll operation selpll 0 1 pll clock selection register after reset: 01h r/w address: fffff806h < > < > < > note for the rtost0 bit, refer to chapter 12 real-time output function (rto) . caution be sure to clear bits 4 to 7 to 0. chan ging bit 3 does not a ffect the operation.
chapter 5 clock generation function preliminary user?s manual u16892ej1v0ud 130 5.5.3 usage (1) when pll is used ? ? ? ?
preliminary user?s manual u16892ej1v0ud 131 chapter 6 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850es/ke1 incorporates tmp0. 6.1 overview an outline of tmp0 is shown below. ? clock selection: 8 ways ? capture trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 6.2 functions tmp0 has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 132 6.3 configuration tmp0 includes the following hardware. table 6-1. configuration of tmp0 item configuration timer register 16-bit counter registers tmp0 capture/compare registers 0, 1 (tp0ccr0, tp0ccr1) tmp0 counter read buffer register (tp0cnt) ccr0, ccr1 buffer registers timer inputs 2 (tip00 note , tip01 pins) timer outputs 2 (top00, top01 pins) control registers tmp0 control registers 0, 1 (tp0ctl0, tp0ctl1) tmp0 i/o control registers 0 to 2 (tp0ioc0 to tp0ioc2) tmp0 option registers 0, 1 (tp0opt0, tp0opt1) note the tip00 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. figure 6-1. block diagram of tmp0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 selector internal bus internal bus top00 top01 tip00 tip01 selector ccr0 buffer register ccr1 buffer register tp0ccr0 tp0ccr1 16-bit counter tp0cnt inttp0ov inttp0cc0 inttp0cc1 output controller clear edge detector edge detector digital noise eliminator remark f xx : main clock frequency
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 133 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tp0cnt register. when the tp0ctl0.tp0ce bit = 0, the va lue of the 16-bit counter is ffffh. if the tp0cnt register is read at this time, 0000h is read. reset input clears the tp0ce bit to 0. t herefore, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tp0ccr0 register is used as a compare regist er, the value written to the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttp0cc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h, as t he tp0ccr0 register is cleared to 0000h after reset. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tp0ccr1 register is used as a compare regist er, the value written to the tp0ccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttp0cc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h, as t he tp0ccr1 register is cleared to 0000h after reset. (4) edge detector this circuit detects the valid edges input to the tip00 and tip01 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tp0ioc1 and tp0ioc2 registers. (5) output controller this circuit controls the output of the top00 and top0 1 pins. the output contro ller is controlled by the tp0ioc0 register. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. (7) digital noise eliminator this circuit is valid only when the tip0a pi n is used as a capture trigger input pin. this circuit is controlled by the tip0a noise elimination register (panfc). remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 134 6.4 registers (1) tmp0 control re gister 0 (tp0ctl0) the tp0ctl0 register is an 8-bit register that controls the operation of tmp0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tp0ctl0 register by software. tp0ce tmp0 operation disabled (tmp0 reset asynchronously note ). tmp0 operation enabled. tmp0 operation started. tp0ce 0 1 tmp0 operation control tp0ctl0 0 0 0 0 tp0cks2 tp0cks1 tp0cks0 654321 after reset: 00h r/w address: fffff5a0h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tp0cks2 0 0 0 0 1 1 1 1 internal count clock selection tp0cks1 0 0 1 1 0 0 1 1 tp0cks0 0 1 0 1 0 1 0 1 note tp0opt0.tp0ovf bit, 16-bit counter , timer output (top00, top01 pins) cautions 1. set the tp0cks2 to tp0 cks0 bits when the tp0ce bit = 0. when the value of the tp0ce bi t is changed from 0 to 1, the tp0cks2 to tp0cks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to 0. remark f xx : main clock frequency
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 135 (2) tmp0 control re gister 1 (tp0ctl1) the tp0ctl1 register is an 8-bit register that controls the operation of tmp0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tp0est 0 1 software trigger control tp0ctl1 tp0est tp0eee 0 0 tp0md2 tp0md1 tp0md0 <6> <5> 4 3 2 1 after reset: 00h r/w address: fffff5a1h generate a valid signal for external trigger input. ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 136 (3) tmp0 i/o control register 0 (tp0ioc0) the tp0ioc0 register is an 8-bit register that controls the timer output (top00, top01 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tp0ol1 0 1 top01 pin output level setting top01 pin output inversion disabled top01 pin output inversion enabled tp0ioc0 0 0 0 tp0ol1 tp0oe1 tp0ol0 tp0oe0 6543<2>1 after reset: 00h r/w address: fffff5a2h tp0oe1 0 1 top01 pin output setting timer output disabled ? ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 137 (4) tmp0 i/o control register 1 (tp0ioc1) the tp0ioc1 register is an 8-bit regist er that controls the valid edge of the capture trig ger input signals (tip00, tip01 pins). this register can be read or written in 8-bit units. reset input clears this register to 00h. 0 tp0is3 0 0 1 1 tp0is2 0 1 0 1 capture trigger input signal (tip01 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tp0ioc1 0 0 0 tp0is3 tp0is2 tp0is1 tp0is0 654321 after reset: 00h r/w address: fffff5a3h tp0is1 0 0 1 1 tp0is0 0 1 0 1 capture trigger input signal (tip00 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tp0is3 to tp0is0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. the tp0is3 to tp0is0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible.
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 138 (5) tmp0 i/o control register 2 (tp0ioc2) the tp0ioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tip00 pin) and external trigger input signal (tip00 pin). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tp0ees1 0 0 1 1 tp0ees0 0 1 0 1 external event count input signal (tip00 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tp0ioc2 0 0 0 tp0ees1 tp0ees0 tp0ets1 tp0ets0 654321 after reset: 00h r/w address: fffff5a4h tp0ets1 0 0 1 1 tp0ets0 0 1 0 1 external trigger input signal (tip00 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tp0ees1, tp0ees0, tp0ets1, and tp0ets0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. the tp0ees1 and tp0ees0 bi ts are valid only when the tp0ctl1.tp0eee bit = 1 or when the external event count mode (tp0ctl1.tp0md2 to tp0ctl1.tp0md0 bits = 001) has been set.
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 139 (6) tmp0 option register 0 (tp0opt0) the tp0opt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tp0ccs1 0 1 tp0ccr1 register capture/compare selection the tp0ccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tp0opt0 0 tp0ccs1 tp0ccs0 0 0 0 tp0ovf 654321 after reset: 00h r/w address: fffff5a5h tp0ccs0 0 1 tp0ccr0 register capture/compare selection the tp0ccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tp0ovf set (1) reset (0) tmp0 overflow detection flag the tp0ovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. an interrupt request signal (inttp0ov) is generated at the same time that the tp0ovf bit is set to 1. the inttp0ov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. the tp0ovf bit is not cleared even when the tp0ovf bit or the tp0opt0 register is read when the tp0ovf bit = 1. the tp0ovf bit can be both read and written, but the tp0ovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmp0. overflow occurred tp0ovf bit 0 written or tp0ctl0.tp0ce bit = 0 7 <0> cautions 1. rewrite the tp0ccs1 and tp0ccs0 bits when the tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mi stakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to 0.
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 140 (7) tmp0 capture/compare register 0 (tp0ccr0) the tp0ccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tp0opt0.tp0ccs0 bit. in the pulse width measurement mode, the tp0ccr0 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tp0ccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tp0ccr0 register is disable d during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff5a6h 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 141 (a) function as compare register the tp0ccr0 register can be rewritten even when the tp0ctl0.tp0ce bit = 1. the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttp0cc0) is generated. if top00 pin output is ena bled at this time, the output of the top00 pin is inverted. when the tp0ccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. (b) function as capture register when the tp0ccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tp0ccr0 register if the valid ed ge of the capture trigger input pin (tip00 pin) is detected. in the pulse width measur ement mode, the count value of the 16-bit counter is stored in the tp0ccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tip00 pin) is detected. even if the capture operation and reading the tp0 ccr0 register conflict, the correct value of the tp0ccr0 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 6-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 142 (8) tmp0 capture/compare register 1 (tp0ccr1) the tp0ccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tp0opt0.tp0ccs1 bit. in the pulse width measurement mode, the tp0ccr1 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tp0ccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tp0ccr1 register is disable d during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff5a8h 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 143 (a) function as compare register the tp0ccr1 register can be rewritten even when the tp0ctl0.tp0ce bit = 1. the set value of the tp0ccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttp0cc1) is generated. if top01 pin output is ena bled at this time, the output of the top01 pin is inverted. (b) function as capture register when the tp0ccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tp0ccr1 register if the valid ed ge of the capture trigger input pin (tip01 pin) is detected. in the pulse width measur ement mode, the count value of the 16-bit counter is stored in the tp0ccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tip01 pin) is detected. even if the capture operation and reading the tp0 ccr1 register conflict, the correct value of the tp0ccr1 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 6-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 144 (9) tmp0 counter read buffer register (tp0cnt) the tp0cnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tp0ctl0.tp0ce bit = 1, the count value of the 16-bit counter can be read. this register is read-only, in 16-bit units. the value of the tp0cnt register is cleared to 0000h wh en the tp0ce bit = 0. if t he tp0cnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tp0cnt register is cleared to 000 0h, as the tp0ce bit is cleared to 0 after reset. caution accessing the tp0cnt register is disabl ed during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff5aah 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 145 6.5 operation tmp0 can perform the following operations. operation tp0ctl1.tp0est bit (software trigger bit) tip00 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that t he valid edge of the tip00 pin capture trigger input is not detected (by clearing the tp0ioc1.tp0i s1 and tp0ioc1.tp0is0 bits to ?00?). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tp0ctl1.tp0eee bit to 0).
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 146 6.5.1 interval timer mode (t p0md2 to tp0md0 bits = 000) in the interval timer mode, an interrupt request signal (inttp0cc0) is generated at t he specified interval if the tp0ctl0.tp0ce bit is set to 1. a square wave whose hal f cycle is equal to the interval can be output from the top00 pin. usually, the tp0ccr1 register is not used in the interval timer mode. figure 6-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tp0ce bit tp0ccr0 register count clock selection clear match signal top00 pin inttp0cc0 signal figure 6-3. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1)
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 147 when the tp0ce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the top00 pin is inverted. additionally, the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the top00 pin is in verted, and a compare match interrupt request signal (inttp0cc0) is generated. the interval can be calculated by the following expression. interval = (set value of tp0ccr0 register + 1)
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 148 figure 6-4. register setting for in terval timer mode operation (2/2) (d) tmp0 counter read buffer register (tp0cnt) by reading the tp0cnt register, the count va lue of the 16-bit counter can be read. (e) tmp0 capture/compare register 0 (tp0ccr0) if the tp0ccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1)
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 149 (1) interval timer mode operation flow figure 6-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ccr0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 150 (2) interval timer mode operation timing (a) operation if tp0ccr0 register is cleared to 0000h if the tp0ccr0 register is cleared to 0000h, the inttp 0cc0 signal is generated at each count clock, and the output of the top00 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 151 (b) operation if tp0ccr0 register is set to ffffh if the tp0ccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. t he counter is cleared to 0000h in synchronization with the next count-up timing. the inttp0cc0 signal is generated and the output of the top00 pin is inverted. at this time, an overflow interrupt request signal (inttp0ov) is not generated, nor is the overflow flag (tp0opt0.tp0ovf bit) set to 1. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal ffffh interval time 10000h
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 152 (c) notes on rewriting tp0ccr0 register to change the value of the tp0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tp0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register tp0ol0 bit top00 pin output inttp0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remark interval time (1): (d 1 + 1)
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 153 (d) operation of tp0ccr1 register figure 6-6. configuration of tp0ccr1 register ccr0 buffer register tp0ccr0 register tp0ccr1 register ccr1 buffer register top00 pin inttp0cc0 signal top01 pin inttp0cc1 signal 16-bit counter output controller tp0ce bit count clock selection clear match signal output controller match signal
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 154 if the set value of the tp0ccr1 register is less than the set value of the tp0ccr0 register, the inttp0cc1 signal is generated once per cycle. at the same time, the output of t he top01 pin is inverted. the top01 pin outputs a square wave with the sa me cycle as that output by the top00 pin. figure 6-7. timing chart when d 01
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 155 if the set value of the tp0ccr1 register is greater than the set value of the tp0ccr0 register, the count value of the 16-bit counter does not match the va lue of the tp0ccr1 register. consequently, the inttp0cc1 signal is not generated, nor is the output of the top01 pin changed. figure 6-8. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 156 6.5.2 external event count mode (tp0md2 to tp0md0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tp0ctl0.tp0ce bit is set to 1, and an interrupt request si gnal (inttp0cc0) is generated each time the specified number of edges have been counted . the top00 pin cannot be used. usually, the tp0ccr1 register is not us ed in the external event count mode. figure 6-9. configuration in external event count mode 16-bit counter ccr0 buffer register tp0ce bit tp0ccr0 register edge detector clear match signal inttp0cc0 signal tip00 pin (external event count input) figure 6-10. basic timing in external event count mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 0 d 0 d 0 d 0 16-bit counter tp0ccr0 register inttp0cc0 signal external event count input (tip00 pin input) d 0 external event count interval (d 0 + 1) d 0 ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 157 when the tp0ce bit is set to 1, the value of the 16-bit counter is clea red from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttp0cc0) is generated. the inttp0cc0 signal is generated each time the valid e dge of the external event count input has been detected (set value of tp0ccr0 register + 1) times. figure 6-11. register setting for operati on in external event count mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 0: stop counting 1: enable counting 000 tp0cks2 tp0cks1 tp0cks0 tp0ce (b) tmp0 control register 1 (tp0ctl1) 00000 tp0ctl1 0, 0, 1: external event count mode 001 tp0md2 tp0md1 tp0md0 tp0eee tp0est (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0 0 tp0oe1 tp0ol0 tp0oe0 tp0ol1 (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 158 figure 6-11. register setting for operati on in external event count mode (2/2) (e) tmp0 counter read buffer register (tp0cnt) the count value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register 0 (tp0ccr0) if d 0 is set to the tp0ccr0 register, the counter is cleared and a compare match interrupt request signal (inttp0cc0) is generated when the nu mber of external event counts reaches (d 0 + 1). (g) tmp0 capture/compare register 1 (tp0ccr1) usually, the tp0ccr1 register is not used in the exte rnal event count mode. however, the set value of the tp0ccr1 register is transferred to the ccr1 buff er register. when the count value of the 16-bit counter matches the value of the ccr1 buffer re gister, a compare match interrupt request signal (inttp0cc1) is generated. therefore, mask the interrupt signal by using the interrupt mask flag (tp0ccmk1). remark tmp0 i/o control register 1 (tp0ioc1) and tmp0 option register 0 (tp0opt0) are not used in the external event count mode.
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 159 (1) external event count mode operation flow figure 6-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 160 (2) operation timing in external event count mode (a) operation if tp0ccr0 register is cleared to 0000h if the tp0ccr0 register is cleared to 0000h, the in ttp0cc0 signal is generated each time the valid edge of the external event count signal has been detected. the 16-bit counter is always 0000h. external event count signal 16-bit counter tp0ce bit tp0ccr0 register inttp0cc0 signal 0000h external event count signal interval external event count signal interval external event count signal interval ffffh 0000h 0000h 0000h 0000h (b) operation if tp0ccr0 register is set to ffffh if the tp0ccr0 register is set to ffffh, the 16-bit co unter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttp0cc0 signal is generated. at this time, the tp0opt0.tp0ovf bit is not set. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 161 (c) notes on rewriting the tp0ccr0 register to change the value of the tp0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tp0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) if the value of the tp0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tp0ccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttp0cc0 signal is generated. therefore, the inttp0cc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?.
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 162 (d) operation of tp0ccr1 register figure 6-13. configuration of tp0ccr1 register ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller top01 pin inttp0cc1 signal edge detector tip00 pin if the set value of the tp0ccr1 register is smalle r than the set value of the tp0ccr0 register, the inttp0cc1 signal is generated once per cycle. at the same time, the output signal of the top01 pin is inverted. figure 6-14. timing chart when d 01
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 163 if the set value of the tp0ccr1 register is greater than the set value of the tp0ccr0 register, the inttp0cc1 signal is not generated because the count va lue of the 16-bit counte r and the value of the tp0ccr1 register do not match. nor is t he output signal of t he top01 pin changed. figure 6-15. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 164 6.5.3 external trigger pulse output mode (tp0md2 to tp0md0 bits = 010) in the external trigger pulse output mode, 16-bit timer/event counter p waits for a trigger when the tp0ctl0.tp0ce bit is set to 1. when the valid edge of an ex ternal trigger input signal is detected, 16-bit timer/event counter p starts counting, and outputs a pwm waveform from the top01 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the top00 pin. figure 6-16. configuration in external trigger pulse output mode ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) output controller top01 pin inttp0cc1 signal top00 pin count clock selection count start control edge detector software trigger generation tip00 pin transfer transfer s r
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 165 figure 6-17. basic timing in exte rnal trigger pulse output mode external trigger input (tip00 pin input) top00 pin output (software trigger) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output 16-bit timer/event counter p waits for a trigger when the tp0c e bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the top01 pin. if the trigger is generated again while the counter is opera ting, the counter is cleared to 0000h and restarted. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tp0ccr1 register)
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 166 figure 6-18. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0/1 0/1 0 0 tp0ctl1 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count with external event input signal generate software trigger when 1 is written 010 tp0md2 tp0md1 tp0md0 tp0eee tp0est 0, 1, 0: external trigger pulse output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output settings of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 167 figure 6-18. setting of registers in exte rnal trigger pulse output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the cycle and active level width of the pwm waveform are as follows. cycle = (d 0 + 1)
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 168 (1) operation flow in extern al trigger pulse output mode figure 6-19. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) top00 pin output (software trigger) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5>
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 169 figure 6-19. software processing flow in ex ternal trigger pulse output mode (2/2) tp0ce bit = 1 setting of tp0ccr0 register register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting is enabled (tp0ce bit = 1). trigger wait status tp0ccr1 register write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. start setting of tp0ccr1 register <1> count operation start flow <2> tp0ccr0 and tp0ccr1 register setting change flow setting of tp0ccr0 register when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. setting of tp0ccr1 register <4> tp0ccr0, tp0ccr1 register setting change flow only writing of the tp0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. setting of tp0ccr1 register <3> tp0ccr0, tp0ccr1 register setting change flow tp0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 170 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tp0ccr1 register last. rewrite the tp0ccra register after writing the tp0ccr1 register after the inttp0cc0 signal is detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) top00 pin output (software trigger) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 171 in order to transfer data from the tp0ccra register to the ccra buffer register, the tp0ccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tp0ccr0 register and then set the active level width to the tp0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tp0ccr0 register, and then write the same value to the tp0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tp0ccr1 register has to be set. after data is written to the tp0ccr1 register, the val ue written to the tp0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tp0ccr0 or tp0ccr1 register again after writing the tp0ccr1 register once, do so after the inttp0cc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tp0ccra register to the ccra buffer register conflicts with writing the tp0ccra register. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 172 (b) 0%/100% output of pwm waveform to output a 0% waveform, clear the tp0ccr1 register to 0000h. if the set value of the tp0ccr0 register is ffffh, the inttp0cc1 signal is generated periodically. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 173 (c) conflict between trigger detecti on and match with tp0ccr1 register if the trigger is detected immediately after the inttp 0cc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the top01 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 1 ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 174 (d) conflict between trigger detecti on and match with tp0ccr0 register if the trigger is detected immediately after the inttp 0cc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the top01 pin is extended by time from generation of the inttp0cc0 signal to trigger detection. 16-bit counter tp0ccr0 register inttp0cc0 signal top01 pin output external trigger input (tip00 pin input) d 0 d 0 ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 175 (e) generation timing of compare match interrupt request signal (inttp0cc1) the timing of generation of the inttp0cc1 signal in the external trigger pulse output mode differs from the timing of other inttp0cc1 signals; the inttp0cc1 signal is generated when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 176 6.5.4 one-shot pulse output mode (tp0md2 to tp0md0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter p waits for a trigger when the tp0ctl0.tp0ce bit is set to 1. when the valid edge of an external trigger input is detected, 16-bit timer/event co unter p starts counting, and outputs a one-shot pulse from the top01 pin. instead of the external trigger, a software trigger can also be generated to output the pulse. when the software trigger is used, the top00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 6-20. configuration in one-shot pulse output mode ccr0 buffer register tp0ce bit tp0ccr0 register tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) top01 pin inttp0cc1 signal top00 pin count clock selection count start control edge detector software trigger generation tip00 pin transfer transfer s r output controller (rs-ff) s r 16-bit counter
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 177 figure 6-21. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 178 figure 6-22. setting of registers in one-shot pulse output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0/1 0/1 0 0 tp0ctl1 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tp0md2 tp0md1 tp0md0 tp0eee tp0est 0, 1, 1: one-shot pulse output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 179 figure 6-22. setting of registers in one-shot pulse output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 1 ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 180 (1) operation flow in one-shot pulse output mode figure 6-23. software processing flow in one-shot pulse output mode <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). trigger wait status count operation is stopped start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 0 d 0 d 1 d 1 d 0
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 181 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tp0ccra register to change the set value of the tp0ccra register to a smaller value, stop counting once, and then change the set value. if the value of the tp0ccra register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 delay (d 10 ) active level width (d 00 ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 182 (b) generation timing of compare match interrupt request signal (inttp0cc1) the generation timing of the inttp0cc1 signal in the on e-shot pulse output mode is different from other inttp0cc1 signals; the inttp0cc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 183 6.5.5 pwm output mode (tp0md2 to tp0md0 bits = 100) in the pwm output mode, a pwm waveform is output from the top01 pin when the tp0ctl0.tp0ce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the top00 pin. figure 6-24. configuration in pwm output mode ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) output controller top01 pin inttp0cc1 signal top00 pin count clock selection count start control transfer transfer s r
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 184 figure 6-25. basic timing in pwm output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal top00 pin output tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 185 figure 6-26. register setting in pwm output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 00000 tp0ctl1 100 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 0, 0: pwm output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 186 figure 6-26. register setting in pwm output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input. 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the cycle and active level width of the pwm waveform are as follows. cycle = (d 0 + 1)
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 187 (1) operation flow in pwm output mode figure 6-27. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal top00 pin output tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> <3> <4> <5> <1>
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 188 figure 6-27. software processing flow in pwm output mode (2/2) tp0ce bit = 1 setting of tp0ccr0 register register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting is enabled (tp0ce bit = 1). tp0ccr1 write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. start setting of tp0ccr1 register <1> count operation start flow <2> tp0ccr0, tp0ccr1 register setting change flow setting of tp0ccr0 register when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tp0ccr1 register <4> tp0ccr0, tp0ccr1 register setting change flow only writing of the tp0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tp0ccr1 register <3> tp0ccr0, tp0ccr1 register setting change flow tp0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 189 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tp0ccr1 register last. rewrite the tp0ccra register after writing the tp0ccr1 register after the inttp0cc1 signal is detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register tp0ccr1 register ccr1 buffer register top01 pin output inttp0cc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tp0ccra register to the ccra buffer register, the tp0ccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tp0ccr0 register and then set the active level width to the tp0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tp0ccr0 register, and then write the same value to the tp0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tp0ccr1 register has to be set. after data is written to the tp0ccr1 register, the val ue written to the tp0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tp0ccr0 or tp0ccr1 register again after writing the tp0ccr1 register once, do so after the inttp0cc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tp0ccra register to the ccra buffer register conflicts with writing the tp0ccra register. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 190 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tp0ccr1 register to 0000h. if the set value of the tp0ccr0 register is ffffh, the inttp0cc1 signal is generated periodically. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 191 (c) generation timing of compare match interrupt request signal (inttp0cc1) the timing of generation of the inttp0cc1 signal in the pwm output mode differs from the timing of other inttp0cc1 signals; the inttp0cc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 192 6.5.6 free-running timer mode (tp0md2 to tp0md0 bits = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tp 0ctl0.tp0ce bit is set to 1. at this time, the tp0ccra register can be used as a compare register or a c apture register, depending on the setting of the tp0opt0.tp0ccs 0 and tp0opt0.tp0ccs1 bits. figure 6-28. configuration in free-running timer mode tp0ccr0 register (capture) tp0ce bit tp0ccr1 register (capture) 16-bit counter tp0ccr1 register (compare) tp0ccr0 register (compare) output controller tp0ccs0, tp0ccs1 bits (capture/compare selection) top00 pin output output controller top01 pin output edge detector count clock selection digital noise eliminator digital noise eliminator tip00 pin (external event count input/ capture trigger input) tip01 pin (capture trigger input) internal count clock 0 1 0 1 inttp0ov signal inttp0cc1 signal inttp0cc0 signal edge detector edge detector remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 193 when the tp0ce bit is set to 1, 16-bit timer/event counter p starts counting, and the ou tput signals of the top00 and top01 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tp0ccra register, a compare match interrupt request signal (inttp0 cca) is generated, and the out put signal of the top0a pin is inverted. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttp0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tp0opt0.tp0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tp0ccra register can be rewritten whil e the counter is operating. if it is re written, the new value is reflected at that time, and compared with the count value. figure 6-29. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 194 when the tp0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tip0a pin is detected, the count value of the 16-bit counter is stored in the tp0ccra register, and a capture interrupt request signal (inttp0cca) is generated. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttp0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tp0opt0.tp0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 6-30. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 195 figure 6-31. register setting in free-running timer mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 101 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 0, 1: free-running mode 0: operate with count clock selected by tp0cks0 to tp0cks2 bits 1: count on external event count input signal (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level with operation of top00 pin disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 196 figure 6-31. register setting in free-running timer mode (2/2) (d) tmp0 i/o control register 1 (tp0ioc1) 0 0 0 0 0/1 tp0ioc1 select valid edge of tip00 pin input select valid edge of tip01 pin input 0/1 0/1 0/1 tp0is2 tp0is1 tp0is0 tp0is3 (e) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (f) tmp0 option register 0 (tp0opt0) 0 0 0/1 0/1 0 tp0opt0 overflow flag specifies if tp0ccr0 register functions as capture or compare register specifies if tp0ccr1 register functions as capture or compare register 0 0 0/1 tp0ccs0 tp0ovf tp0ccs1 (g) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (h) tmp0 capture/compare regist ers 0 and 1 (tp0ccr0 and tp0ccr1) these registers function as captur e registers or compare registers depending on the setting of the tp0opt0.tp0ccsa bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to t he tip0a pin is detected. when the registers function as compare registers and when d a is set to the tp0ccra register, the inttp0cca signal is generated when the counter reaches (d a + 1), and the output signal of the top0a pin is inverted. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 197 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 6-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3>
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 198 figure 6-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tp0ce bit = 1 read tp0opt0 register (check overflow flag). register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0opt0 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). start execute instruction to clear tp0ovf bit (clr tp0ovf). <1> count operation start flow <2> overflow flag clear flow tp0ce bit = 0 counter is initialized and counting is stopped by clearing tp0ce bit to 0. stop <3> count operation stop flow tp0ovf bit = 1 no yes
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 199 (b) when using capture/compare register as capture register figure 6-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2>
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 200 figure 6-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tp0ce bit = 1 read tp0opt0 register (check overflow flag). register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc1 register, tp0opt0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). start execute instruction to clear tp0ovf bit (clr tp0ovf). <1> count operation start flow <2> overflow flag clear flow tp0ce bit = 0 counter is initialized and counting is stopped by clearing tp0ce bit to 0. stop <3> count operation stop flow tp0ovf bit = 1 no yes
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 201 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an interval timer with the tp0ccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttp0cca signal has been detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? ? ? ? ? ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 202 (b) pulse width measurement with capture register when pulse width measurement is performed with the tp0ccra register used as a capture register, software processing is necessary for reading the capt ure register each time the inttp0cca signal has been detected and for calculating an interval. ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? ? ? ? ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 203 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register tip01 pin input tp0ccr1 register inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> read the tp0ccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 204 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tp0ce bit inttp0ov signal tp0ovf bit tp0ovf0 flag note tip00 pin input tp0ccr0 register tp0ovf1 flag note tip01 pin input tp0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tp0ovf0 and tp0ovf1 flags are set on the internal ram by software. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> an overflow occurs. set the tp0ovf0 and tp0ovf 1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tp0ccr0 register. read the tp0ovf0 flag. if the tp0ovf0 flag is 1, clear it to 0. because the tp0ovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 205 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tp0ce bit inttp0ov signal tp0ovf bit tp0ovf0 flag note tip00 pin input tp0ccr0 register tp0ovf1 flag note tip01 pin input tp0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tp0ovf0 and tp0ovf1 flags are set on the internal ram by software. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tp0ccr0 register. read the overflow flag. if the overflow flag is 1, set only the tp0ovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 206 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0ov signal tp0ovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tp0ccra register (setting of t he default value of the tip0a pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tp0ccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d a1 ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 207 example when capture trigger interval is long ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0ov signal tp0ovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tp0ccra register (setting of t he default value of the tip0a pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tp0ccra register. read the overflow counter.
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 208 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tp0ovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tp0opt0 regist er. to accurately detect an overflow, read the tp0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tp0ovf bit) overflow flag (tp0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction.
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 209 6.5.7 pulse width measurement mode (tp0md2 to tp0md0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter p starts counting when the tp0ctl0.tp0ce bit is set to 1. each time the valid edge input to the tip0a pi n has been detected, the count va lue of the 16-bit counter is stored in the tp0ccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readin g the tp0ccra register after a capture interrupt request signal (inttp0cca) occurs. select either the tip00 or tip01 pin as the capture trigger input pin. specify ?no edge detected? by using the tp0ioc1 register for the unused pins. when an external clock is used as the count clock, measur e the pulse width of the tip01 pin because the external clock is fixed to the tip00 pin. at this time, clear the tp0ioc1.tp0is1 and tp0ioc1.tp0is0 bits to 00 (capture trigger input (tip00 pin): no edge detected). figure 6-34. configuration in pulse width measurement mode tp0ccr0 register (capture) tp0ce bit tp0ccr1 register (capture) edge detector count clock selection edge detector edge detector tip00 pin (external event count input/capture trigger input) tip01 pin (capture trigger input) internal count clock clear inttp0ov signal inttp0cc0 signal inttp0cc1 signal 16-bit counter digital noise eliminator digital noise eliminator remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 210 figure 6-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0cca signal inttp0ov signal tp0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark a = 0, 1 when the tp0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tip0a pin is later detected, the count value of the 16-bit counter is stored in the tp0ccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttp0cca) is generated. the pulse width is calculated as follows. first pulse width = (d 0 + 1) ? ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 211 figure 6-36. register setting in pu lse width measurement mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note setting is invalid when the tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 110 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tp0cks0 to tp0cks2 bits 1: count external event count input signal (c) tmp0 i/o control register 1 (tp0ioc1) 0 0 0 0 0/1 tp0ioc1 select valid edge of tip00 pin input select valid edge of tip01 pin input 0/1 0/1 0/1 tp0is2 tp0is1 tp0is0 tp0is3 (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 212 figure 6-36. register setting in pu lse width measurement mode (2/2) (e) tmp0 option register 0 (tp0opt0) 00000 tp0opt0 overflow flag 0 0 0/1 tp0ccs0 tp0ovf tp0ccs1 (f) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (g) tmp0 capture/compare regist ers 0 and 1 (tp0ccr0 and tp0ccr1) these registers store the count valu e of the 16-bit counter when the valid edge input to the tip0a pin is detected. remarks 1. tmp0 i/o control register 0 (tp0ioc0) is not used in the pulse wid th measurement mode. 2. a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 213 (1) operation flow in pul se width measurement mode figure 6-37. software processing flow in pulse width measurement mode <1> <2> set tp0ctl0 register (tp0ce bit = 1) tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits), tp0ctl1 register, tp0ioc1 register, tp0ioc2 register, tp0opt0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal d 0 0000h 0000h d 1 d 2
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 214 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tp0ovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tp0opt0 regist er. to accurately detect an overflow, read the tp0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tp0ovf bit) overflow flag (tp0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction.
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 215 6.5.8 timer output operations the following table shows the operations and out put levels of the top00 and top01 pins. table 6-4. timer output control in each mode operation mode top01 pin top00 pin interval timer mode square wave output external event count mode square wave output ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 216 6.6 eliminating noise on capture trigger input pin (tip0a) the tip0a pin has a digital noise eliminator. however, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is used as an external event count input pin or external trigger input pin. digital noise can be eliminated by specifying the alter nate function of the tip0a pi n using the pmc3, pfc3, and pfce3 registers. the number of times of sampling can be selected from three or two by using the panfc.panfsts bit. the sampling clock can be selected from f xx , f xx /2, f xx /4, f xx /16, f xx /32, or f xx /64, by using the panfc.panfc2 to panfc.panfc0 bits. (1) tip0a noise elimination control register (panfc) this register is used to select the sampling clock and t he number of times of sampling for eliminating digital noise. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 panfc (a = 0, 1) panfsts 0 0 0 panfc2 panfc1 panfc0 number of times of sampling = 3 number of times of sampling = 2 panfsts 0 1 setting of number of times of sampling for eliminating digital noise after reset: 00h r/w address: p0nfc fffffb00h, p1nfc fffffb04h f xx f xx /2 f xx /4 f xx /16 f xx /32 f xx /64 panfc2 0 0 0 0 1 1 panfc1 0 0 1 1 0 0 panfc0 0 1 0 1 0 1 sampling clock selection setting prohibited other than above cautions 1. enable starting the 16-bit counter of tmp0 (tp0ctl.tp0ce bit = 1) after the lapse of the sampling clock period
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 217 <1> select the number of times of sampling a nd the sampling clock by using the panfc register. <2> select the alternate function (of the tip0a pin) by using the pmc3, pfc3, and pfce3 registers. <3> set the operating mode of tmp0 (such as the capt ure mode or the valid edge of the capture trigger). <4> enable the tmp0 count operation. the digital noise elimination width (t wtipa ) is as follows, where t is the sampling clock period and m is the number of times of sampling. ? ? ? ? ?
chapter 6 16-bit timer/event counter p (tmp) preliminary user?s manual u16892ej1v0ud 218 6.7 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh, not 0000h, may be captured in the tp0ccrn register if the capture trigger is input immediately after the tp0ce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tp0ce bit tp0ccr0 register ffffh 0001h 0000h tip00 pin input capture trigger input 16-bit counter sampling clock capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tp0ce bit tp0ccr0 register tip00 pin input capture trigger input 16-bit counter sampling clock capture trigger input
preliminary user?s manual u16892ej1v0ud 219 chapter 7 16-bit timer/event counter 0 in the v850es/ke1, one channel of 16-bit timer/event counter 0 is provided. 7.1 functions 16-bit timer/event counter 01 has the following functions. (1) interval timer generates an interrupt at predetermined time intervals. (2) ppg output can output a rectangular wave with any frequency and any output pulse width. (3) pulse width measurement can measure the pulse width of a signal input from an external source. (4) external event counter can measure the number of pulses of a signal input from an external source. (5) square-wave output can output a square wave of any frequency. (6) one-shot pulse output can output a one-shot pulse wit h any output pulse width.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 220 7.2 configuration 16-bit timer/event counter 01 consis ts of the following hardware. table 7-1. configuration of 16-bit timer/event counter 01 item configuration timer/counters 16-bi t timer counter 01 1 (tm01) registers 16-bit timer captur e/compare register: 16 bits 2 (cr010, cr011) timer inputs 2 (ti010, ti011 pins) timer outputs 1 (to01 pin), output controller control registers note 16-bit timer mode control register 01 (tmc01) capture/compare control register 01 (crc01) 16-bit timer output control register 01 (toc01) prescaler mode register 01 (prm01) note to use the ti010, ti011, and to01 pin functions, refer to table 4-12 settings when port pins are used for alternate functions .
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 221 the block diagram is shown below. figure 7-1. block diagram of 16-bit timer/event counter 01 inttm010 to01 inttm011 tl011 f xx /4 tl010 2 crc012 prm011 crc012 crc011 crc010 prm010 tmc013 tmc012 tmc011 ovf01 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 match clear noise eliminator noise eliminator 16-bit timer capture/compare register 010 (cr010) 16-bit timer capture/compare register 011 (cr011) 16-bit timer counter 01 (tm01) match internal bus count clock note capture/compare control register 01 (crc01) output controller selector timer output control register 01 (toc01) noise eliminator prescaler mode register 01 (prm01) 16-bit timer mode control register 01 (tmc01) selector selector internal bus selector note set with the prm01 register. remark f xx : main clock frequency
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 222 (1) 16-bit timer counter 01 (tm01) the tm01 register is a 16-bit read-onl y register that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. tm01 12 10 8 6 4 2 after reset: 0000h r address: fffff610h 14 0 13 11 9 7 5 3 15 1 the count value is reset to 0000h in the following cases. <1> reset <2> if the tmc01.tmc013 and tmc01.tmc012 bits are cleared (0) <3> if the valid edge of the ti010 pin is input in the mode in which clear & start occurs when inputting the valid edge of the ti010 pin <4> if the tm01 register and the cr010 register match eac h other in the mode in which clear & start occurs on a match between the tm01 register and the cr010 register <5> if the toc01.ospt01 bit is set (1) in the one-shot pulse output mode (2) 16-bit timer capture/comp are register 010 (cr010) the cr010 register is a 16-bit register that combines capture register and compare register functions. the crc01.crc010 bit is used to set whether to use the cr010 register as a ca pture register or as a compare register. the cr010 register can be read or written in 16-bit units. after reset, this register is cleared to 0000h. cr010 12108642 after reset: 0000h r/w address: fffff612h 14 0 13 11 9 7 5 3 15 1
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 223 (a) when using the cr010 register as a compare register the value set to the cr010 register and the count value set to the tm01 register are always compared and when these values match, an interrupt request si gnal (inttm010) is generated. the values are retained until rewritten. (b) when using the cr010 register as a capture register the tm01 register count value is captured to the cr010 register by inputting a capture trigger. the valid edge of the ti010 pin or ti011 pin can be selected as the captur e trigger. the valid edge of the ti010 pin is set with the prm01.es1 01 and prm01.es100 bits. the va lid edge of the ti011 pin is set with the prm01.es111 and prm01.es110 bits. table 7-2 shows the settings when the valid edge of the ti010 pin is specified as the capture trigger, and table 7-3 shows the settings when the valid edge of the ti011 pin is specified as the capture trigger. table 7-2. capture trigger of cr010 register and valid edge of ti010 pin capture trigger of cr010 valid edge of ti010 pin es101 es100 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 remark setting the es101 and es100 bits to 10 is prohibited. table 7-3. capture trigger of cr010 register and valid edge of ti011 pin capture trigger of cr010 valid edge of ti011 pin es111 es110 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remark setting the es111 and es110 bits to 10 is prohibited. cautions 1. set a value other than 0000h to the cr010 register in the mode in which clear & start occurs upon a match of the values of th e tm01 register and cr010 register. however, if 0000h is set to the cr010 regist er in the free-running timer mode or the ti010 pin valid edge clear & start mode, an interrupt request signal (inttm010) is generated when the value cha nges from 0000h to 0001h afte r an overflow (ffffh). 2. when the p35 pin is u sed as the valid edge of ti010, it cannot be used as timer output (to01). moreover, when used as to 01, the pin cannot be used as the valid edge of ti010. 3. if, when the cr010 register is used as a capture register , the register read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. the cr010 register cannot be rewri tten during timer count operation.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 224 (3) 16-bit timer capture/comp are register 011 (cr011) the cr011 register is a 16-bit register that combines capture register and compare register functions. the crc01.crc012 bit is used to set whether to use the cr011 register as a capture re gister or as a compare register. the cr011 register can be read or written in 16-bit units. after reset, this register is cleared to 0000h. cr011 12 10 8 6 4 2 after reset: 0000h r/w address: fffff614h 14 0 13 11 9 7 5 3 15 1 (a) when using the cr011 register as a compare register the value set to the cr011 regist er and the count value of the tm 01 register are always compared and when these values match, an interrupt re quest signal (inttm011) is generated. (b) when using the cr011 register as a capture register the tm01 register count value is captured to the cr011 register by inputting a capture trigger. the valid edge of the ti010 pin can be selected as the capture trigger. the valid edge of the ti010 pin is set with the prm01.es101 and prm01.es100 bits. table 7-4 shows the settings when the valid edge of t he ti010 pin is specified as the capture trigger. table 7-4. capture trigger of cr011 register and valid edge of ti010 pin capture trigger of cr011 valid edge of ti010 pin es101 es100 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remark setting the es101 and es100 bits to 10 is prohibited. cautions 1. if 0000h is set to the cr011 regist er, an interrupt request signal (inttm011) is generated after overflow of the tm01 regist er, after clear & start on a match between the tm01 register and cr010 register, after cl ear by the valid edge of the ti010 pin, or after clear by a one-shot pulse output trigger. 2. when the p35 pin is u sed as the valid edge of ti010, it cannot be used as timer output (to01). moreover, when used as to 01, the pin cannot be used as the valid edge of ti010. 3. if, when the cr011 register is used as a capture register , the register read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. the cr011 register can be rewritten dur ing tm01 register operation only in the ppg output mode. refer to 7.4.2 ppg output operation.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 225 7.3 registers the registers that control 16-bit time r/event counter 01 are as follows. ? ? ? ?
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 226 7 0 operation stop (tm01 cleared to 0) free-running timer mode clear & start with valid edge of ti010 clear & start upon match of tm01 and cr010 unchanged match of tm01 and cr010 or match of tm01 and cr011 ? match of tm01 and cr010 or match of tm01 and cr011 not generated generated upon match of tm01 and cr010 and match of tm01 and cr011 tmc013 0 0 1 1 selection of operation mode and clear mode selection of to01 output inverse timing 6 0 5 0 4 0 3 tmc013 2 tmc012 1 tmc011 note <0> ovf01 tmc012 0 1 0 1 tmc011 note 0 0 0 0 after reset: 00h r/w address: fffff616h no overflow overflow ovf01 0 1 detection of overflow of 16-bit timer register 01 tmc01 generation of interrupt setting prohibited other than above note be sure to clear the tmc011 bit to 0. cautions 1. write to bits other than the ov f01 flag after stopping the timer operation. 2. the valid edge of the ti010 pi n is set by the prm01 register. 3. when the mode in which the timer is cleared and started upon match of tm01 and cr010 is selected, the setting value of cr 010 is ffffh, and when the value of tm01 changes from ffffh to 0000h, the ovf01 flag is set to 1. remark to01: output pin of 16-b it timer/event counter 01 ti010: input pin of 16-bit timer/event counter 01 tm01: 16-bit timer counter 01 cr010: 16-bit timer capture/compare register 010 cr011: 16-bit timer capture/compare register 011 the following shows the i/o c onfiguration of each ch annel and the selection of the to01 output inversion timing (setting of the tmc011 bit). table 7-5. i/o configuration of each channel channel output pin input pin i/o pin setting of tmc011 bit tm01 ? ti011 ti010/to01 always clear to 0.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 227 (2) capture/compare control register 01 (crc01) the crc01 register controls the operation of the cr010 and cr011 registers. the crc01 register can be read or written in 8-bit or 1-bit units. after reset, crc01 is cleared to 00h. 7 0 operation as compare register operation as capture register crc012 0 1 selection of operation mode of cr011 register crc01 6 0 5 0 4 0 3 0 2 crc012 1 crc011 0 crc010 after reset: 00h r/w address: fffff618h capture at valid edge of ti011 pin capture at inverse phase of valid edge of ti010 pin crc011 0 1 selection of capture trigger of cr010 register operation as compare register operation as capture register crc010 0 1 selection of operation mode of cr010 register cautions 1. before setting the crc01 regist er, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started upon match of the tm01 register and cr010 register is selected by the tmc01 register , do not specify the cr010 register as the capture register. 3. when both the rising and falling edges are specified for the ti010 pin valid edge, capture operation is not performed. 4. to ensure reliable capture operation, a pulse longer than tw o cycles of the count clock selected by the prm01 register is required.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 228 (3) 16-bit timer output control register 01 (toc01) the toc01 register controls the operation of the 16-bit timer/event counter 01 output controller by setting or resetting the timer output f/f, enabling or disabling inve rse output, enabling or disabling the timer of 16-bit timer/event counter 01, enabling or disabling the one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software. the toc01 register can be read or written in 8-bit or 1-bit units. after reset, toc01 is cleared to 00h. (1/2) 0 ? one-shot pulse output ospt01 note 1 0 1 output trigger for one-shot pulse by software toc01 ospt01 note 1 ospe01 note 1 toc014 lvs01 lvr01 toc011 toe01 successive pulse output one-shot pulse output note 2 ospe01 note 1 0 1 control of one-shot pulse output operation inversion operation disabled inversion operation enabled toc014 0 1 control of timer output f/f upon match of cr011 register and tm01 register after reset: 00h r/w address: fffff619h 7 <6> <5> 4 <3> <2> 1 <0> unchanged reset timer output f/f (0) set timer output f/f (1) setting prohibited lvs01 0 0 1 1 setting of status of timer output f/f lvr01 0 1 0 1 notes 1. 16-bit timer/event counter 01 is the alternate-function pin of the timer i/o pin, so only a software trigger is valid for one-shot pulse output. clear the tmc01.tmc011 bit to 0. 2. the one-shot pulse output operates normally only in the free-running timer mode. in the mode in which clear & start occurs on match betw een the tm01 register and the cr010 register, one- shot pulse output is not performed because no overflow occurs.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 229 (2/2) inversion operation disabled inversion operation enabled toc011 0 1 control of timer output f/f upon match of cr010 register and tm01 register output disabled (output is fixed to low level) output enabled toe01 0 1 control of timer output cautions 1. be sure to stop the timer operat ion before setting other than the toc014 bit. 2. the lvs01 and lvr01 bits are 0 when read. 3. the ospt01 bit is 0 when read because it is automatically cleared after data has been set. 4. do not set the ospt01 bit to 1 other than for one-shot pulse output. 5. when performing successi ve writes to the ospt01 bit, place an interval between writes of two or more cycles of the coun t clock selected by the prm01 register. 6. do not set the lvs01 bit to 1 before setting the toe01 bit. do not set the lvs01 bit and toe01 bit to 1 at the same time. 7. do not set <1> and <2> below at the same time. set as follows. <1> set the toc011, toc014, toe01, and ospe01 bits: setting of timer output operation <2> set the lvs01 and lvr01 bits: setting of timer output f/f
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 230 (4) prescaler mode register 01 (prm01) the prm01 register sets the count clock of the tm01 register and the valid edge of the ti010 and ti011 pin inputs. the prm01 register can be read or written in 8-bit or 1-bit units. after reset, prm01 is cleared to 00h. cautions 1. when setting the count clock to the ti 010 pin valid edge, do not set the mode in which clear & start occurs on ti010 pin valid edge and do not set the ti010 pin as the capture trigger. 2. before setting the prm01 register, be sure to stop the timer operation. 3. if 16-bit timer/event counter 01 operation is enabled by specifying the rising edge or both edges for the valid edge of the ti010 pin or ti011 pin while the ti010 pin or ti011 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. be careful when pulling up the ti010 pin or ti011 pin. however, the rising edge is not det ected when operation is enabled after it has been stopped. 4. when the p35 pin is used as the valid edge of ti010, it cannot be used as timer output (to01). moreover, when used as to01, the pin cannot be used as the valid edge of ti010.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 231 es111 falling edge rising edge setting prohibited both rising and falling edges es111 0 0 1 1 selection of valid edge of ti011 prm01 es110 es101 es100 0 0 prm011 prm010 es110 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es101 0 0 1 1 selection of valid edge of ti010 es100 0 1 0 1 f xx f xx /4 intwt valid edge of ti010 note 2 selection of count clock note 1 prm011 0 0 1 1 prm010 0 1 0 1 20 mhz 200 ns ? ? 16 mhz 250 ns ? ? count clock f xx after reset: 00h r/w address: fffff617h 76 54 32 1 0 10 mhz 100 ns 400 ns ? ? setting prohibited setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 232 7.4 operation 7.4.1 operation as interval timer 16-bit timer/event counter 01 can be m ade to operate as an interval timer by setting the tmc01 register and the crc01 register as shown in figure 7-2. setting procedure the basic operation setting procedure is as follows. <1> set the count clock using the prm01 register. <2> set the crc01 register (refer to figure 7-2 for the setting value). <3> set any value to the cr010 register. <4> set the tmc01 register: start operation (refer to figure 7-2 for the setting value). caution the cr010 register cannot be rewritten during 16-bit ti mer/event counter 01 operation. remarks 1. for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttm010 interrupt enable, refer to chapter 17 interrupt/exception processing function . the interval timer repeatedly generates in terrupts at the interval of the preset count value in the cr010 register. if the count value in the tm01 register matches the value set in the cr010 register, an interrupt request signal (inttm010) is generated at the same time that the value of the tm 01 register is cleared to 0000h and counting is continued. the count clock of 16-bit timer/ev ent counter 01 can be selected with the prm01.prm010 and prm01.prm011 bits. figure 7-2. control register settings in interval timer operation (a) 16-bit timer mode control register 01 (tmc01) 0 tmc01 0001100 tmc013 tmc012 tmc011 ovf01 clears & starts upon match between tm01 and cr010 (b) capture/compare cont rol register 01 (crc01) 0 crc01 00000/10/10 crc012 crc011 crc010 cr010 used as compare register remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the interval timer function. for details, refer to 7.3 (2) capture/compare c ontrol register 01 (crc01) .
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 233 figure 7-3. configuration of interval timer 16-bit timer capture/compare register 010 (cr010) 16-bit timer counter 01 (tm01) selector ovf01 inttm010 count clock note ti010 clear circuit noise eliminator f xx /4 note set with the prm01 register. remark f xx : main clock frequency figure 7-4. timing of interval timer operation t interval time interval time 0000h n 0001h 0001h 0000h nn n n n n 0001h 0000h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm01 count value cr010 inttm010 timer operation enable remark interval time = (n + 1)
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 234 7.4.2 ppg output operation 16-bit timer/event counter 01 can be used for ppg (progr ammable pulse generator) ou tput by setting the tmc01 register and the crc01 register as shown in figure 7-5. setting procedure the basic operation setting procedure is as follows. <1> set the crc01 register (refer to figure 7-5 for the setting value). <2> set any value as a cycle to the cr010 register. <3> set any value as a duty to the cr011 register. <4> set the toc01 register (refer to figure 7-5 for the setting value). <5> set the count clock using the prm01 register. <6> set the tmc01 register: start operation (refer to figure 7-5 for the setting value). caution to change the duty value ( cr011 register) during operation, re fer to remark 2 in figure 7-7 ppg output operation timing. remarks 1. for the alternate-function pin (to01) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttm010 interrupt enable, refer to chapter 17 interrupt/exception processing function . the ppg output function outputs a rectangular wave from the to01 pin with the cycle s pecified by the count value set in advance to the cr010 register and the pulse width s pecified by the count value set in advance to the cr011 register.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 235 figure 7-5. control register settings in ppg output operation (a) 16-bit timer mode control register 01 (tmc01) 00001 tmc013 tmc01 tmc012 tmc011 ovf01 clears and starts upon match between tm01 and cr010 100 (b) capture/compare cont rol register 01 (crc01) 00000 crc01 crc012 crc011 crc010 cr010 used as compare register cr011 used as compare register 0 : don't care 0 (c) 16-bit timer output control register 01 (toc01) 0 0 0 1 0/1 toc01 enables to01 output inverts output upon match between tm01 and cr010 specifies initial value of to01 output f/f inverts output upon match between tm01 and cr011 disables one-shot pulse output 0/1 1 1 lvr01 toc011 toe01 ospe01 ospt01 toc014 lvs01 (d) prescaler mode register 01 (prm01) 0/1 0/1 0/1 0/1 0 3 prm01 2 prm011 prm010 es111 es110 es101 es100 selects count clock setting invalid (setting to 10 is prohibited.) setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 cautions 1. make sure that 0000h cr011 < cr010 ffffh is set to the cr010 register and cr011 register. 2. the cycle of the pulse generated by ppg output is (cr010 setting value + 1). the duty factor is (cr011 setting val ue + 1) / (cr010 setting value + 1)
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 236 figure 7-6. configuration of ppg output to01 16-bit capture/compare register 011 (cr011) 16-bit capture/compare register 010 (cr010) count clock note selector 16-bit timer counter 01 (tm01) clear circuit output controller note the count clock is set with the prm01 register.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 237 figure 7-7. ppg output operation timing t 0000h 0000h 0001h 0001h m ? ?
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 238 7.4.3 pulse width measurement the tm01 register can be used to meas ure the pulse widths of the signals input to the ti010 and ti011 pins. measurement can be carried out with 16-b it timer/event counter 01 used in the free-running timer mode or by restarting the timer in synchronization with the edge of the signal input to the ti010 pin. when an interrupt is generated, read the valid capture re gister value. after confi rming the tmc01.ovf01 flag, clear (0) it by software and measure the pulse width. setting procedure the basic operation setting procedure is as follows. <1> set the crc01 register (refer to figures 7-9 , 7-12 , 7-14 , and 7-16 for the setting value). <2> set the count clock using the prm01 register. <3> set the tmc01 register: start operation (refer to figures 7-9 , 7-12 , 7-14 , and 7-16 for the setting value). caution when using two capture regi sters, set the ti010 and ti011 pins. remarks 1. for the alternate-function pin (ti010, ti011) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttm010 and inttm011 interrupt enable, refer to chapter 17 interrupt/exception processing function . figure 7-8. cr011 capture operation with rising edge specified n ? ? ?
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 239 (1) pulse width measurement with free-running timer operation and one capture register if the edge specified by the prm01 regi ster is input to the ti010 pin when 16-bit timer/event counter 01 is operated in the free-running timer mode (refer to figure 7-9 ), the value of the tm01 register is loaded to the cr011 register and an external interrupt request signal (inttm011) is generated. the valid edge is specified by t he prm01.es100 and prm01.es101 bits. the rising edge, falling edge, or both the rising and falling edges can be selected. the valid edge is detected through sampling at a count clock cycle sele cted with the prm01 register, and the capture operation is not perfo rmed until the valid edge is detected twice. as a result, noise with a short pulse width can be eliminated. figure 7-9. control register setti ngs for pulse width measurement with free-running timer operati on and one capture register (when ti010 pin and cr011 register are used) (a) 16-bit timer mode control register 01 (tmc01) 00000 tmc013 tmc01 tmc012 tmc011 ovf01 free-running timer mode 100 (b) capture/compare cont rol register 01 (crc01) 00000 crc01 crc012 crc011 crc010 cr010 used as compare register cr011 used as capture register 1 0/1 0 (c) prescaler mode register 01 (prm01) 0/1 0/1 1 1 0 prm01 selects count clock (setting to 11 is prohibited.) specifies both edges for pulse width detection setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 2 prm011 prm010 es101 es110 es111 es100 3 remark 0/1: when these bits are reset to 0 or set to 1, other functions can be us ed together with the pulse width measurement function. for details, refer to 7.3 (2) capture/compare control register 01 (crc01) .
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 240 figure 7-10. configuration fo r pulse width measurement with free-running timer operation 16-bit timer counter 01 (tm01) 16-bit timer capture/compare register 011 (cr011) selector ovf01 inttm011 internal bus ti010 count clock note note the count clock is set with the prm01 register. figure 7-11. timing of pulse width measu rement with free-running timer operation and one capture register ( with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 + 1 d1 d0 d1 d2 d3 d2 d3 d1 + 1 (d1 ? d0)
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 241 (2) measurement of two pulse width s with free-running timer operation the pulse widths of two signals respectively input to the ti010 pin and the ti011 pi n can be simultaneously measured when 16-bit timer/event counter 01 is used in the free-running timer mode (refer to figure 7-12 ). when the edge specified by the prm 01.es100 and prm01.es101 bits is input to the ti010 pin, the value of the tm01 register is loaded to the cr011 register and an external inte rrupt request signal (inttm011) is generated. when the edge specified by the prm 01.es110 and prm01.es111 bits is input to the ti011 pin, the value of the tm01 register is loaded to the cr010 register and an external inte rrupt request signal (inttm010) is generated. the edges of the ti010 and ti011 pi ns are specified by the prm01. es100 and prm01.es101 bits and the prm01.es110 and prm01.es111 bits, respectively. specify both rising and falling edges. the valid edge of the ti010 pin is det ected through sampling at the count clock cycle selected with the prm01 register, and the capture oper ation is not performed until the valid level is detected twice. as a result, noise with a short pulse width can be eliminated. figure 7-12. control register settings for measurement of two pulse widths with free-running timer operation (a) 16-bit timer mode control register 01 (tmc01) 0 tmc01 0000100 tmc013 tmc012 tmc011 ovf01 free-running timer mode (b) capture/compare cont rol register 01 (crc01) 0 crc01 0000101 crc012 crc011 crc010 cr010 used as capture register captures to cr010 at valid edge of ti011 pin cr011 used as capture register (c) prescaler mode register 01 (prm01) 11110 prm01 selects count clock (setting to 11 is prohibited.) specifies both edges for pulse width detection. specifies both edges for pulse width detection. 0 0/1 0/1 2 prm011 prm010 es101 es110 es111 es100 3
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 242 ?
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 243 (3) pulse width measurement with free-running timer operation and two capture registers when 16-bit timer/event counter 01 is used in the free-running timer mode (refer to figure 7-14 ), the pulse width of the signal input to the ti010 pin can be measured. when the edge specified by the prm 01.es100 and prm01.es101 bits is input to the ti010 pin, the value of the tm01 register is loaded to the cr011 register and an external inte rrupt request signal (inttm011) is generated. the value of the tm01 register is al so loaded to the cr010 register wh en an edge inverse to the one that triggers capturing to the cr011 register is input. the valid edge of the ti010 pin is detected through sampling at a count clock cycle selected with the prm01 register, and the capture operation is not performed until the valid edge is det ected twice. as a result, noise with a short pulse width can be eliminated. figure 7-14. control register setti ngs for pulse width measurement with free-running timer operati on and two capture registers (with rising edge specified) (a) 16-bit timer mode control register 01 (tmc01) 0 tmc01 0000100 tmc013 tmc012 tmc011 ovf01 free-running timer mode (b) capture/compare cont rol register 01 (crc01) 0 crc01 0000111 crc012 crc011 crc010 cr010 used as capture register captures to cr010 at edge inverse to valid edge of ti010 pin cr011 used as capture register (c) prescaler mode register 01 (prm01) 0/1 0/1 0 1 0 3 prm01 2 prm011 prm010 es111 es110 es101 es100 selects count clock (setting to 11 is prohibited.) specifies rising edge of pulse width detection setting invalid (setting to 10 is prohibited.) 0 0/1 0/1
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 244 figure 7-15. timing of pulse width measu rement with free-running timer operation and two capture registers (with rising edge specified) t 0000h 0001h ffffh 0000h d0 d0 d1 d3 d2 d0 + 1 d1 d1 + 1 d2 d3 d2 + 1 (d1 ? d0)
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 245 (4) pulse width measurement by restarting when the valid edge of the ti010 pin is detected, the pulse width of the signal input to the ti010 pin can be measured by clearing the tm01 regist er and then resuming counting after l oading the count value of the tm01 register to the cr011 register (refer to figure 7-17 ). the edge is specified by the prm01.es100 and pr m01.es101 bits. the rising or falling edge can be specified. the valid edge is detected through sa mpling at a count clock cycle select ed with the prm01 register and the capture operation is not performed until the valid level is detected twice. as a result, noise with a short pulse width can be eliminated. figure 7-16. control register settings fo r pulse width measurement by restarting (a) 16-bit timer mode control register 01 (tmc01) 0 tmc01 0001000 tmc013 tmc012 tmc011 ovf01 clears and starts at valid edge of ti010 pin (b) capture/compare cont rol register 01 (crc01) 0 crc01 0000111 crc012 crc011 crc010 cr010 used as capture register captures to cr010 at edge inverse to valid edge of ti010 pin cr011 used as capture register (c) prescaler mode register 01 (prm01) 0/1 0/1 0 1 0 3 prm01 2 prm011 prm010 es111 es110 es101 es100 selects count clock (setting to 11 is prohibited.) specifies rising edge of pulse width detection setting invalid (setting to 10 is prohibited.) 0 0/1 0/1
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 246 figure 7-17. timing of pulse width measurement by restarting (with rising edge specified) t (d1 + 1)
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 247 7.4.4 operation as external event counter setting procedure the basic operation setting procedure is as follows. <1> set the crc01 register (refer to figure 7-18 for the setting value). <2> set the count clock using the prm01 register. <3> set any value (except for 0000h) to the cr010 register. <4> set the tmc01 register: start operation (refer to figure 7-18 for the setting value). remarks 1. for the alternate-function pin (ti010) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttm010 interrupt enable, refer to chapter 17 interrupt/exception processing function . the external event counter counts the number of clock pulses input to the ti010 pin from an external source by using the tm01 register. each time the valid edge specified by the prm01 regist er has been input, the tm01 r egister is incremented. when the count value of the tm01 regist er matches the value of the cr010 r egister, the tm01 register is cleared to 0000h and an interrupt request signal (inttm010) is generated. set the cr010 register to a value other than 0000 h (one-pulse count operation is not possible). the edge is specified by the prm01.es100 and prm01.es 101 bits. the rising, falling, or both the rising and falling edges can be specified. the valid edge is detected through sampling at a count clock cycle of f xx /4, and the capture operation is not performed until the valid level is detected twice. as a re sult, noise with a short pulse width can be eliminated. cautions 1. the timer output (to01) cannot be used. 2. the value of the cr010 and cr011 registers cannot be change d during timer c ount operation.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 248 figure 7-18. control register se ttings in external ev ent count mode (with rising edge specified) (a) 16-bit timer mode control register 01 (tmc01) 00001 tmc013 tmc01 tmc012 tmc011 ovf01 clears and starts on match between tm01 and cr010 100 (b) capture/compare cont rol register 01 (crc01) 00000 crc01 crc012 crc011 crc010 cr010 used as compare register 0/1 0/1 0 (c) prescaler mode register 01 (prm01) 0/1 0/1 0 1 0 3 prm01 2 prm011 prm010 es111 es110 es101 es100 selects external clock specifies rising edge of external event count input setting invalid (setting to 10 is prohibited.) 011 remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the external event counter function. for details, refer to 7.3 (2) capture/compare co ntrol register 01 (crc01) .
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 249 figure 7-19. configuration of external event counter 16-bit timer capture/compare register 010 (cr010) 16-bit timer counter 01 (tm01) 16-bit timer capture/compare register 011 (cr011) selector ovf01 inttm010 count clock note fxx/4 ti010 valid edge internal bus noise eliminator match clear note set with the prm01 register. figure 7-20. timing of external event coun ter operation (with rising edge specified) 0000h 0001h 0002h 0003h 0000h 0001h 0002h 0003h 0004h 0005h n ?
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 250 7.4.5 square-wave output operation setting procedure the basic operation setting procedure is as follows. <1> set the count clock using the prm01 register. <2> set the crc01 register (refer to figure 7-21 for the setting value). <3> set the toc01 register (refer to figure 7-21 for the setting value). <4> set any value (except for 0000h) to the cr010 register. <5> set the tmc01 register: start operation (refer to figure 7-21 for the setting value). remarks 1. for the alternate-function pin (to01) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttm010 interrupt enable, refer to chapter 17 interrupt/exception processing function . 16-bit timer/event counter 01 can be us ed to output a square wave with any fr equency at an interval specified by the count value set in advance to the cr010 register. by setting the toc01.toe01 and toc01.to c011 bits to 11, the out put status of the to01 pin is inverted at an interval set in advance to the cr010 register. in this way, a square wave of any frequency can be output. caution the value of the cr010 and cr011 registers cannot be changed during timer coun t operation.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 251 figure 7-21. control register setti ngs in square-wave output mode (a) 16-bit timer mode control register 01 (tmc01) 00001 tmc013 tmc01 tmc012 tmc011 ovf01 clears and starts upon match between tm01 and cr010 100 (b) capture/compare cont rol register 01 (crc01) 00000 crc01 crc012 crc011 crc010 cr010 used as compare register 0/1 0/1 0 (c) 16-bit timer output control register 01 (toc01) 0 0 0 0 0/1 toc01 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 enables to01 output inverts output upon match between tm01 and cr010 specifies initial value of to01 output f/f does not invert output upon match between tm01 and cr011 disables one-shot pulse output 0/1 1 1 (d) prescaler mode register 01 (prm01) 0/1 0/1 0/1 0/1 0 3 prm01 2 prm011 prm010 es111 es110 es101 es100 selects count clock setting invalid (setting to 10 is prohibited.) setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used together wit h the square- wave output. for details, refer to 7.3 (2) capture/compare c ontrol register 01 (crc01) .
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 252 figure 7-22. timing of square-wave output operation 0000h 0001h 0002h 0000h 0001h 0002h n ? ?
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 253 7.4.6 one-shot pulse output operation 16-bit timer/event counter 01 can output a one-shot pulse in synchronization with a software trigger. a one-shot pulse output by the external trigger input is not available in the v850es/ke1. setting procedure the basic operation setting procedure is as follows. <1> set the count clock using the prm01 register. <2> set the crc01 register (refer to figure 7-23 for the setting value). <3> set the toc01 register (refer to figure 7-23 for the setting value). <4> set any value to the cr010 and cr011 registers. <5> set the tmc01 register: start operation (refer to figure 7-23 for the setting value). remarks 1. for the alternate-function pin (to01) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttm010 interrupt enable, refer to chapter 17 interrupt/exception processing function . a one-shot pulse can be output from the to01 pin by setting the tmc01, crc01, and toc01 registers as shown in figure 7-23, and by setting the toc 01.ospt01 bit to 1 by software. by setting the ospt01 bit to 1, 16-bit timer/event counter 01 is cleared and started, and its output becomes active at the count value (n) set in advance to the cr011 register. after that, the output becomes inactive at the count value (m) set in advance to the cr010 register note . even after the one-shot pulse has been output, 16-bit timer/ event counter 01 continues its operation. to stop 16- bit timer/event counter 01, the tmc01.tmc013 an d tmc01.tmc012 bits must be cleared to 00. note the case where n < m is described here. when n > m, the output becomes acti ve with the cr010 register and inactive with the cr011 register. cautions 1. do not set the ospt01 bit to 1 while the one-shot pulse is being output. to output the one- shot pulse again, wait until the current one-shot pulse output is completed. 2. the value of the cr010 and cr011 registers cannot be change d during timer c ount operation.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 254 figure 7-23. control register settings for one-shot pulse output (1/2) (a) 16-bit timer mode control register 01 (tmc01) 00000 tmc013 tmc01 tmc012 tmc011 ovf01 free-running timer mode 100 (b) capture/compare cont rol register 01 (crc01) 00000 crc01 crc012 crc011 crc010 cr010 used as compare register cr011 used as compare register 0 0/1 0 (c) 16-bit timer output control register 01 (toc01) 0 0 1 1 0/1 toc01 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 enables to01 output inverts output upon match between tm01 and cr010 specifies initial value of to01 output f/f inverts output upon match between tm01 and cr011 sets one-shot pulse output mode set to 1 for output 0/1 1 1
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 255 figure 7-23. control register settings for one-shot pulse output (2/2) (d) prescaler mode register 01 (prm01) 0/1 0/1 0/1 0/1 0 3 prm01 2 prm011 prm010 es111 es110 es101 es100 selects count clock setting invalid (setting to 10 is prohibited.) setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 caution do not set 0000h to the cr010 and cr011 registers. remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the one- shot pulse output. for details, refer to 7.3 (2) capture/compare control register 01 (crc01) . figure 7-24. timing of one-shot pulse output operation 0000h n nn n n mm m m nm n + 1 n ? 1m ? 1 0001h m + 1 m + 2 0000h count clock tm01 count cr011 set value cr010 set value ospt01 inttm011 inttm010 to01 pin output when tmc01 register is set to 04h caution 16-bit timer counter 01 starts operating as soon as a value other than 00 (operation stop mode) is set to the tmc013 and tmc012 bits. remark n < m
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 256 7.4.7 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the count of the tm01 register is st arted asynchronously to the count pulse. figure 7-25. count start timing of tm01 register 0000h timer start 0001h 0002h 0003h 0004h count pulse tm01 count value (2) setting cr010 and cr011 registers (in the mode in which clear & start occurs upon match between tm01 register and cr010 register) set the cr010 and cr011 registers to a value other th an 0000h (when using these registers as external event counters, one-pulse count operation is not possible). (3) data hold timing of capture register <1> if the valid edge of the ti010 pin is input while t he cr011 register is read, the cr011 register performs capture operation, but the read value at this time is not guarant eed. however, the interrupt request signal (inttm011) is generated as a result of detection of the valid edge. figure 7-26. data hold timing of capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm01 count value edge input inttm011 cr011 capture value capture read signal capture operation is performed but read value is not guaranteed capture operation <2> the values of the cr010 and cr011 registers are not guaranteed after 16-bit timer/event counter 01 has stopped.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 257 (4) setting valid edge before setting the valid edge of the ti010 pin, stop the timer operation by clear ing the tmc01.tmc012 and tmc01.tmc013 bits to 00. set the valid edge by using the prm01.es100 and prm01.es101 bits. (5) re-triggering one-shot pulse when a one-shot pulse is output, do not set the ospt01 bit to 1. do not output t he one-shot pulse again until the inttm010 signal, which occurs upon match with the cr010 register, or the inttm011 signal, which occurs upon match with the cr011 register, occurs. (6) operation of ovf01 flag (a) setting of ovf01 flag the tmc01.ovf01 flag is set to 1 in the following case in addition to when the tm01 register overflows. select the mode in which clear & start occurs upon match between the tm01 r egister and the cr010 register. set the cr010 register to ffffh when the tm01 register is cleared from ffffh to 0000h upon match with the cr010 register figure 7-27. operation timing of ovf01 flag fffeh ffffh ffffh 0000h 0001h count pulse tm01 inttm010 ovf01 cr010 (b) clearing of ovf01 flag after the tm01 register overflows, clearing ovf01 fl ag is invalid and set (1) again even if the ovf01 flag is cleared (0) before the next count clock is c ounted (before the tm01 regi ster becomes 0001h).
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 258 (7) timer operation (a) cr011 register capture even if the tm01 register is read, the read data cannot be captured into the cr011 register. (b) ti010, ti011 pin acknowledgment regardless of the cpu?s operation mode, if the time r is stopped, signals input to the ti010 and ti011 pins are not acknowledged. (c) one-shot pulse output one-shot pulse output oper ates normally only in the free-runnin g timer mode. because no overflow occurs in the mode in which clear & start occurs upon match between the tm01 register and the cr010 register, one-shot pulse output is not possible. (8) capture operation (a) if valid edge of ti010 is specified for count clock if the valid edge of ti010 is specified for the count clo ck, the capture register t hat specified ti010 as the trigger does not operate normally. (b) if both rising and fa lling edges are selected for valid edge of ti010 if both the rising and falling edges are selected for t he valid edge of ti010, capture operation is not performed. (c) to ensure that signals from ti 011 and ti010 are correctly captured for the capture trigger to capture the signals from ti011 and ti010 correc tly, a pulse longer than two of the count clocks selected by the prm01 register is required. (d) interrupt request input although a capture operation is per formed at the falling edge of the count clock, an interrupt request signal (inttm010, inttm011) is generated at t he rising edge of the next count clock. (9) compare operation when set to the compare mode, the cr010 and cr011 re gisters do not perform capt ure operation even if a capture trigger is input. caution the value of the cr010 register cannot be changed during timer operati on. the value of the cr011 register cannot be changed during timer ope ration other than in the ppg output mode. to change the cr011 register in the ppg output mode, refer to 7.4.2 ppg output operation.
chapter 7 16-bit timer/event counter 0 preliminary user?s manual u16892ej1v0ud 259 (10) edge detection (a) sampling clock for noise elimination the sampling clock for noise elimination differs dep ending on whether the valid edge of ti010 is used for the count clock or as a capture trigger. in the former case, sampling is performed using f xx /4, and in the latter case, sampling is performed using the count clo ck selected by the prm01 register. the first capture operation does not start until the va lid edges are sampled and two valid levels are detected, thus eliminating noise with a short pulse width. remark f xx : main clock frequency
preliminary user?s manual u16892ej1v0ud 260 chapter 8 8-bit timer/event counter 5 in the v850es/ke1, two channels of 8-bi t timer/event counter 5 are provided. 8.1 functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1). ? ? ? ? ? ? ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 261 figure 8-1. block diagram of 8-bit timer/event counter 5n ovf ti5n 3 tcl5n2 tcl5n1 tcl5n0 tce5n tmc5n6 tmc5n4 lvs5n lvr5n tmc5n1 toe5n to5n inttm5n s r q inv s r q match clear count clock note selector internal bus internal bus 8-bit timer mode control register 5n (tmc5n) 8-bit timer compare register 5n (cr5n) 8-bit timer counter 5n (tm5n) selector invert level mask circuit timer clock selection register 5n (tcl5n) selector selector note the count clock is set by the tcl5n register. remark n = 0, 1 8.2 configuration 8-bit timer/event counter 5n consists of the following hardware. table 8-1. configuration of 8-bit timer/event counter 5n item configuration timer registers 8-bit timer counter 5n (tm5n) 16-bit timer counter 5 (tm5): on ly when using cascade connection registers 8-bit timer compare register 5n (cr5n) 16-bit timer compare register 5 (cr5 ): only when using cascade connection timer output 1 (to5n pin) control registers note timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) 16-bit timer mode control register 5 (t mc5): only when using cascade connection note when using the functions of the ti5n and to5n pins, refer to table 4-12 settings when port pins are used for alternate functions . remark n = 0, 1
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 262 (1) 8-bit timer counter 5n (tm5n) the tm5n register is an 8-bit read-only re gister that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. through cascade connection, the tm5n registers can be used as a 16-bit timer. when using the tm50 register and the tm51 register in ca scade as a 16-bit timer, these registers can be read only in 16-bit units. therefore, r ead these registers twice and compare t he values, taking into consideration that the reading occurs during a count change. tm5n (n = 0, 1) 642 after reset: 00h r address: tm50 fffff5c0h, tm51 fffff5c1h 0 753 1 the count value is reset to 00h in the following cases. <1> reset <2> when the tmc5n.tce5n bit is cleared (0) <3> the tm5n register and cr5n register match in t he mode in which clear & start occurs on a match between the tm5n register and the cr5n register caution when connected in cascade, these registers become 0000h ev en when the tce50 bit in the lowest timer (tm50) is cleared. remark n = 0, 1
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 263 (2) 8-bit timer compare register 5n (cr5n) the cr5n register can be read and written in 8-bit units. in a mode other than the pwm mode, the value set to the cr5n register is always compared to the count value of the tm5n register, and if the two values match, an interrupt request signal (inttm5n) is generated. in the pwm mode, tm5n register overfl ow causes the to5n pin output to chan ge to the active level, and when the values of the tm5n register and the cr5n register match, the to5n pi n output changes to the inactive level. the value of the cr5n register can be set in the range of 00h to ffh. when using the tm50 register and tm51 register in ca scade as a 16-bit timer, the cr50 register and cr51 register operate as 16-bit timer compare register 5 (cr5 ). the counter value and register value are compared in 16-bit lengths, and if they match, an inte rrupt request signal (inttm50) is generated. cr5n (n = 0, 1) 642 after reset: 00h r/w address: cr50 fffff5c2h, cr51 fffff5c3h 0 753 1 cautions 1. in the mode in which clear & start occurs upon a match of the tm5n register and cr5n register (tmc5n.tmc5n6 bit = 0), do not writ e a different value to the cr5n register during the count operation. 2. in the pwm mode, set the cr5n register re write interval to thr ee or more count clocks (clock selected with the tcl5n register). 3. before changing the value of the cr5n re gister when using a cascade connection, be sure to stop the timer operation. remark n = 0, 1
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 264 8.3 registers the following two registers are used to co ntrol 8-bit timer/event counter 5n. ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 265 (2) 8-bit timer mode control register 5n (tmc5n) the tmc5n register performs the following six settings. ? ? ? ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 266 tce5n counting is disabled after the counter is cleared to 0 (counter disabled) start count operation tce5n 0 1 control of count operation of 8-bit timer/event counter 5n tmc5n (n = 0, 1) tmc5n6 0 tmc514 note lvs5n lvr5n tmc5n1 toe5n mode in which clear & start occurs on match between tm5n register and cr5n register pwm (free-running timer) mode tmc5n6 0 1 selection of operation mode of 8-bit timer/event counter 5n individual mode cascade connection mode (connected with 8-bit timer/event counter 50) tmc514 0 1 selection of individual mode or cascade connection mode for 8-bit timer/event counter 51 unchanged reset timer output f/f to 0 set timer output f/f to 1 setting prohibited lvs5n 0 0 1 1 setting of status of timer output f/f lvr5n 0 1 0 1 after reset: 00h r/w address: tmc50 fffff5c6h, tmc51 fffff5c7h disable inversion operation enable inversion operation high active low active tmc5n1 0 1 other than pwm (free-running timer) mode (tmc5n6 bit = 0) controls timer f/f pwm (free-running timer) mode (tmc5n6 bit = 1) selects active level disable output (to5n pin is low level) enable output toe5n 0 1 timer output control <7> 6 5 4 <3> <2> 1 <0> note bit 4 of the tmc50 register is fixed to 0. cautions 1. because the to51 and ti51 pins are al ternate functions of the same pin, only one can be used at one time. 2. the lvs5n and lvr5n bit settings are val id in modes other than the pwm mode. 3. do not set <1> to <4> below at the same time. set as follows. <1> set the tmc5n1 , tmc5n6, and tmc514 note bits: setting of operation mode <2> set the toe5n bit for timer output enable: timer output enable <3> set the lvs5n and lvr5n bits (caution 2): setting of timer output f/f <4> set the tce5n bit remarks 1. in the pwm mode, the pwm output is set to the inactive level by the tce5n bit = 0. 2. when the lvs5n and lvr5n bits are read, 0 is read. 3. the values of the tmc5n6, l vs5n, lvr5n, tmc5n1, and toe 5n bits are reflected to the to5n output regardless of the tce5n bit value.
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 267 8.4 operation 8.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer t hat repeatedly generates interrupt s at the interval of the count value preset in the cr 5n register. if the count value in the tm5n register matches the value set in the cr5n register, the value of the tm5n register is cleared to 00h and counting is continued, and at the same time, an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 268 figure 8-2. timing of interval timer operation (2/2) when cr5n register = 00h t interval time 00h 00h 00h 00h 00h count clock tm5n count value cr5n tce5n inttm5n remark n = 0, 1 when cr5n register = ffh t 01h 00h feh ffh 00h feh ffh 00h ffh ffh ffh count clock tm5n count value cr5n tce5n inttm5n interval time interrupt acknowledgment interrupt acknowledgment remark n = 0, 1
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 269 8.4.2 operation as external event counter the external event counter c ounts the number of clock pulses input to the ti5n pin from an external source by using the tm5n register. each time the valid edge specified by the tcl5n register is input to the ti5n pin, the tm5n register is incremented. either the rising edge or the falling e dge can be specified as the valid edge. when the count value of the tm5n regist er matches the value of the cr5n regi ster, the tm5n register is cleared to 00h and an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? ? ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 270 8.4.3 square-wave output operation a square wave with any frequency can be output at an interval determined by the value preset in the cr5n register. by setting the tmc5n.toe5n bit to 1, the output status of the to5n pin is inverted at an interval determined by the count value preset in the cr 5n register. in this way, a square wave of any frequency can be output (duty = 50%) (n = 0, 1). setting method <1> set each register. ? ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 271 figure 8-4. timing of square-wave output operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm5n count value cr5n to5n note tce5n inttm5n count start note the initial value of the to5n pin output can be set using the tmc5n.lvs5n and tmc5n.lvr5n bits. remark n = 0, 1
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 272 8.4.4 8-bit pwm output operation by setting the tmc5n.tmc5n6 bit to 1, 8-bit ti mer/event counter 5n performs pwm output. pulses with a duty factor determined by the value set in the cr5n register are out put from the to5n pin. set the width of the active level of the pwm pulse in t he cr5n register. the active level can be selected using the tmc5n.tmc5n1 bit. the count clock can be select ed using the tcl5n register. pwm output can be enabled/disabled by the tmc5n.toe5n bit. caution the cr5n register rewrite interval must be three or more operation clocks (set by the tcl5n register). use method <1> set each register. ? ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 273 (a) basic operation of pwm output figure 8-5. timing of pwm output operation basic operation (active level = h) 00h n + 1 n n 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h active level inactive level active level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = 00h 00h n + 1 n + 2 n 00h 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = ffh 00h n + 1 n + 2 n ffh 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level inactive level active level active level count clock tm5n count value cr5n tce5n inttm5n to5n t remark n = 0, 1
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 274 (b) operation based on cr5n register transitions figure 8-6. timing of operation b ased on cr5n register transitions when the value of the cr5n register changes from n to m before the rising edge of the ffh clock + + + + + + + + + + + +
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 275 8.4.5 operation as inter val timer (16 bits) the 16-bit resolution timer/event counter mode is se lected by setting the tmc51.tmc514 bit to 1. 8-bit timer/event counter 5n operates as an interval time r by repeatedly generating inte rrupts using the count value preset in 16-bit timer compare register 5 (cr5) as the interval. setting method <1> set each register. ? ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 276 figure 8-7 shows a timing example of the cascade connection mode with 16-bit resolution. figure 8-7. cascade connection mode with 16-bit resolution 00h n + 1 01h 00h ffh 00h 01h ffh 00h ffh m ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 277 8.4.6 operation as external event counter (16 bits) the 16-bit resolution timer/event counter mode is selected by setting the tmc51.tmc514 bit to 1. the external event counter counts the number of clock pulse s input to the ti50 pin from an external source using 16-bit timer counter 5 (tm5). setting method <1> set each register. ? ? ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 278 8.4.7 square-wave output operat ion (16-bit resolution) the 16-bit resolution timer/event counter mode is se lected by setting the tmc51.tmc514 bit to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (cr5). setting method <1> set each register. ? ? ? ? ?
chapter 8 8-bit timer/event counter 5 preliminary user?s manual u16892ej1v0ud 279 8.4.8 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the tm5n register is started a synchronously to the count pulse. figure 8-8. count start timing of tm5n register 00h timer start 01h 02h 03h 04h count pulse tm5n count value remark n = 0, 1
preliminary user?s manual u16892ej1v0ud 280 chapter 9 8-bit timer h in the v850es/ke1, two channels of 8-bit timer h are provided. 9.1 functions 8-bit timer hn has the following functions (n = 0, 1). ? interval timer ? pwm output ? square wave output ? carrier generator mode 9.2 configuration 8-bit timer hn consists of the following hardware. table 9-1. configuration of 8-bit timer hn item configuration timer registers 8-bit ti mer counter hn: 1 each registers 8-bit timer h compare register n0 (cmpn0): 1 each 8-bit timer h compare register n1 (cmpn1): 1 each timer outputs 1 each (tohn pin) control registers note 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) note to use the tohn pin function, refer to table 4-12 settings when port pins are used for alternate functions . remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 281 the block diagram is shown below. figure 9-1. block diag ram of 8-bit timer hn match selector internal bus tmhen ckshn2 ckshn1 ckshn0 tmmdn1tmmdn0 tolevn toenn decoder 8-bit timer h compare register n0 (cmpn0) reload/ interrupt control tohn inttmhn inttm5n selector rmc n nrzb n f xx f xx /2 f xx /2 2 f xx /2 4 f xx /2 6 f xx /2 10 f xt interrupt generator output controller level inversion nrz n 1 0 f/f r 8-bit timer counter hn carrier generator mode signal pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register n1 (cmpn1) 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 282 (1) 8-bit timer h compare register n0 (cmpn0) the cmpn0 register can be read or written in 8-bit units. after reset, cmpn0 is cleared to 00h. cmpn0 (n = 0, 1) after reset: 00h r/w address: cmp00 fffff582h, cmp10 fffff592h 76 54 32 1 0 caution rewriting the cmpn0 register during timer count operation is prohibited. (2) 8-bit timer h compare register n1 (cmpn1) the cmpn1 register can be read or written in 8-bit units. after reset, cmpn1 is cleared to 00h. cmpn1 (n = 0, 1) after reset: 00h r/w address: cmp01 fffff583h, cmp11 fffff593h 76 54 32 1 0 the cmpn1 register can be rewritt en during timer count operation. in the carrier generator mode, after the cmpn1 register is set, if the count value of 8-bit timer counter hn and the set value of the cmpn1 register match, an interrupt request signal (in ttmhn) is generated. at the same time, the value of 8-bit timer counter hn is cleared to 00h. if the set value of the cmpn1 register is rewritten dur ing timer operation, the reload timing is when the count value of 8-bit timer counter hn and the set value of the cmpn1 register match. if the transfer timing and write to the cmpn1 register from the cpu conflict, transfer is not performed. caution in the pwm output mode a nd carrier generator mode, be su re to set the cmpn1 register when starting the timer count operation (t mhmdn.tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register).
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 283 9.3 registers the registers that control 8-bit timer hn are as follows. ? ?
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 284 (a) 8-bit timer h mode register 0 (tmhmd0) tmhe0 stop timer count operation (8-bit timer counter h0 = 00h) enable timer count operation (counting starts when clock is input) tmhe0 0 1 8-bit timer h0 operation enable tmhmd0 cksh02 cksh01 cksh00 tmmd01 tmmd00 tolev0 toen0 after reset: 00h r/w address: fffff580h f xx f xx /2 f xx /4 f xx /16 f xx /64 f xx /1024 cksh02 0 0 0 0 1 1 cksh01 0 0 1 1 0 0 cksh00 0 1 0 1 0 1 setting prohibited 125 ns 250 ns 1 s 4 s 64 s selection of count clock count clock note interval timer mode carrier generator mode pwm output mode setting prohibited tmmd01 0 0 1 1 tmmd00 0 1 0 1 8-bit timer h0 operation mode other than above low level high level tolev0 0 1 timer output level control (default) disable output enable output toen0 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 <1> <0>
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 285 (b) 8-bit timer h mode register 1 (tmhmd1) tmhe1 stop timer count operation (8-bit timer counter h1 = 00h) enable timer count operation (counting starts when clock is input) tmhe1 0 1 8-bit timer h1 operation enable tmhmd1 cksh12 cksh11 cksh10 tmmd11 tmmd10 tolev1 toen1 after reset: 00h r/w address: fffff590h f xx f xx /2 f xx /4 f xx /16 f xx /64 cksh12 0 0 0 0 1 1 cksh11 0 0 1 1 0 0 cksh10 0 1 0 1 0 1 setting prohibited 125 ns 250 ns 1 s 4 s selection of count clock count clock note interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 8-bit timer h1 operation mode f xt (subclock) setting prohibited other than above low level high level tolev1 0 1 timer output level control (default) disable output enable output toen1 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 <1> <0>
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 286 (2) 8-bit timer h carrier cont rol register n (tmcycn) this register controls the 8-bit timer hn remote control output and carrier pulse output status. the tmcycn register can be read or written in 8-bit or 1-bit units. the nrzn bit is a read-only bit. after reset, tmcycn is cleared to 00h. remark n = 0, 1 0 tmcycn (n = 0, 1) 0 0 0 0 rmcn nrzbn nrzn after reset: 00h r/w address: tmcyc0 fffff581h, tmcyc1 fffff591h low-level output high-level output low-level output carrier pulse output rmcn 0 0 1 1 nrzbn 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enable status nrzn 0 1 carrier pulse output status flag 76 54 32 1<0>
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 287 9.4 operation 9.4.1 operation as interval timer/square wave output when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. the cmpn1 register cannot be used in the interval timer mode. even if the cmpn1 register is set, this has no effect on the timer output because matches between 8-bit timer counter hn and the cmpn1 regi ster are not detected. a square wave of the desired frequency (duty = 50%) is out put from the tohn pin, by setting the tmhmdn.toenn bit to 1. (1) usage method the inttmhn signal is repeatedly generated in the same interval. <1> set each register. figure 9-2. register settings in interval timer mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 0 sets timer output sets timer output level inversion sets interval timer mode selects count clock (f cnt ) stops count operation 0 0/1 0/1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register settings ?
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 288 (2) timing chart the timing in the interval timer mode is as follows. figure 9-3. timing of interval timer/ square wave output operation (1/2) basic operation 00h count clock count start 8-bit timer counter hn count value cmpn0 tmhen inttmhn tohn 01h n clear clear n 00h 01h n 00h 01h 00h <1> <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <3> interval time <1> when the tmhen bit is set to 1, the count operation is enabled. the count clock starts counting no more than one clock after operation has been enabled. <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, the value of 8-bit timer counter hn is cleared, the tohn output level is inverted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive when the tmhen bit is cleared to 0 during 8-bit timer hn operation. if the level is al ready inactive, it remains unchanged. remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 289 figure 9-3. timing of interval timer/ square wave output operation (2/2) operation when cmpn0 = ffh 00h count clock count start cmpn0 tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time 8-bit timer counter hn count value operation when cmpn0 = 00h count clock count start cmpn0 tmhen inttmhn tohn 00h 00h interval time 8-bit timer counter hn count value remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 290 9.4.2 pwm output mode operation in the pwm output mode, a pulse of any duty and cycle can be output. the cmpn0 register controls the time r output (tohn) cycle. rewriting the cmpn0 register during timer operation is prohibited. the cmpn1 register controls the time r output (tohn) duty. the cmpn1 r egister can be rewritten during timer operation. the operation in the pwm out put mode is as follows. after timer counting starts, when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, the tohn output becomes active and 8-bit timer count er hn is cleared to 00h. when the count value of 8-bit timer counter hn and the set value of the cmpn1 re gister match, tohn output becomes inactive. (1) usage method in the pwm output mode, a pulse of any duty and cycle can be output. <1> set each register. figure 9-4. register settings in pwm output mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 1 enables timer output sets timer output level inversion selects pwm output mode selects count clock (f cnt ) stops count operation 0 0/1 1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register setting ? ?
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 291 <3> after the count operation is enabled, the first compare register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, 8-bit timer counter hn is cleared, an interrupt request si gnal (inttmhn) is generated, and the tohn output becomes active. at the same time, the register t hat is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <4> when the count value of 8-bit timer counter hn and the set value of the cmpn1 register match, the tohn output becomes inactive, and at the same time the register that is compared with 8-bit timer counter hn changes from the cmpn1 r egister to the cmpn0 register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> a pulse of any duty can be obtained throug h the repetition of steps <3> and <4> above. <6> to stop the count operation, clear the tmhen bit to 0. designating the set value of the cmpn0 register as (n ), the set value of the cm pn1 register as (m), and the count clock frequency as f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n + 1)/f cnt duty = inactive width: active width = (m + 1) : (n + 1) cautions 1. in the pwm output mode, three opera ting clocks (signal selected by ckshn0 to ckshn2 bits) are required for actual transfer of the new value to the register after the cmpn1 register has been rewritten. 2. be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register).
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 292 (2) timing chart the operation timing in the pwm out put mode is as follows. caution the set value (m) of the cm pn1 register and the set value (n ) of the cmpn0 register must always be set within th e following range. 00h
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 293 figure 9-5. operation timing in pwm output mode (2/4) operation when cmpn0 = ffh, cmpn1 = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmpn1 ffh 00h 8-bit timer counter hn count value operation when cmpn0 = ffh, cmpn1 = feh count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmpn1 ffh feh 8-bit timer counter hn count value remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 294 figure 9-5. operation timing in pwm output mode (3/4) operation when cmpn0 = 01h, cmpn1 = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmpn1 00h 8-bit timer counter hn count value remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 295 figure 9-5. operation timing in pwm output mode (4/4) operation based on cmpn1 transitions (cmpn1 = 01h
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 296 9.4.3 carrier genera tor mode operation the carrier clock generated by 8-bit timer hn is output using the cycle set with 8-bit timer/event counter 5n. in the carrier generator mode, 8-bit timer/ event counter 5n is used to control the extent to wh ich the carrier pulse of 8-bit timer hn is output, and the carrier pulse is output from the tohn output. (1) carrier generation in the carrier generator mode, the cmpn0 register gener ates a waveform with the low-level width of the carrier pulse and the cmpn1 register generates a waveform with the high-level width of the carrier pulse. during 8-bit timer hn operation, the cmpn1 register can be rewritten, but rewriting of the cmpn0 register is prohibited. (2) carrier output control carrier output control is performed wit h the interrupt request signal (inttm 5n) of 8-bit timer/event counter 5n and the tmcycn.nrzbn and tmcycn.rmcn bits. t he output relationships are as follows. rmcn bit nrzbn bit output 0 0 low-level output 0 1 high-level output 1 0 low-level output 1 1 carrier pulse output remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 297 to control carrier pulse output during count operati on, the tmcycn.nrzn and tm cycn.nrzbn bits have a master and slave bit configuration. the nrzn bit is read-only while the nrzbn bit can be read and written. the inttm5n signal is synchronized with the 8-bit timer hn clock and output as the inttm5hn signal. the inttm5hn signal becomes the data transfer signal of the nrzn bit and the value of the nrzbn bit is transferred to the nrzn bit. the transfer timing from the nrzbn bit to the nrzn bit is as follows. figure 9-6. transfer timing 8-bit timer hn count clock tmhen inttm5n inttm5hn nrzn nrzbn rmcn 1 1 1 0 00 <1> <2> <1> the inttm5n signal is synchronized with the count clock of 8-bit timer hn and is output as the inttm5hn signal. <2> the value of the nrzbn bit is transferred to the nrzn bit at the second clock from the rising edge of the inttm5hn signal. cautions 1. do not rewrite the nrzbn bit again until at least the second cl ock after it has been rewritten, or else transfer from the nrzbn bit to the nrzn bit is not guaranteed. 2. when using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. an interrupt o ccurs at a different timing when it is used in other than the carrier generator mode. remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 298 (3) usage method any carrier clock can be output from the tohn pin. <1> set each register. figure 9-7. register settings in carrier generator mode ? ? ? ? ?
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 299 designating the set value of the cmpn0 register as (n ), the set value of the cm pn1 register as (m), and the count clock frequency as f cnt , the carrier clock output cycle and duty are as follows. carrier clock output cycle = (n + m + 2)/f cnt duty = high level width: carrier clock out put width = (m + 1) : (n + m + 2) caution be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation w as stopped (tmhen bit = 0) (b e sure to set again even if setting the same value to the cmpn1 register). (4) timing chart the carrier output control timing is as follows. cautions 1. set the values of the cmpn0 and cm pn1 registers in the range of 01h to ffh. 2. in the carrier generator mode, thr ee operating clocks (signal selected by the tmhmdn.ckshn0 to tmhmdn.cks hn2 bits) are required for actual transfer of the new value to the register after the cmpn 1 register has been rewritten. 3. be sure to perform the tmcycn.rmcn bit se tting before the start of the count operation. 4. when using the carrier generator mode, set the 8-bit timer hn c ount clock frequency to six times the 8-bit timer/ event counter 5n count clock frequency or higher.
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 300 figure 9-8. carrier ge nerator mode (1/3) operation when cmpn0 = n, cmpn1 = n is set cmpn0 cmpn1 tmhen inttmhn carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 5n count clock tm5n count value cr5n tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l l inttm5hn <1> <2> <3> <4> <5> <6> <7> 8-bit timer hn count clock 8-bit timer counter hn count value <1> when the tmhen bit = 0 and the tce5n bit = 0, the operation of 8-bit timer hn is stopped. <2> when the tmhen bit is set to 1, 8-bit timer hn starts c ounting. the carrier clock is maintained inactive at this time. <3> when the count value of 8-bit timer counter hn and th e set value of the cmpn0 r egister match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register t hat is compared with 8-bit timer counter hn changes from the cm pn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is invert ed, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a duty of 50% is generated through the repetition of steps <3> and <4>. <5> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the inttm5hn signal becomes the data transfer signal of the nrzbn bit, and the va lue of the nrzbn bit is transferred to the nrzn bit. <7> the tohn output is made low leve l by clearing the nrzn bit = 0. remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 301 figure 9-8. carrier ge nerator mode (2/3) operation when cmpn0 = n, cmpn1 = m is set n l cmpn0 cmpn1 tmhen inttmhn carrier clock tm5n count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m cr5n tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l inttm5hn <1> <2> <3> <4> <5> <6> <7> 8-bit timer 5n count clock 8-bit timer hn count clock 8-bit timer counter hn count value <1> when the tmhen bit = 0 and the tce5n bit = 0, the operation of 8-bit timer hn is stopped. <2> when the tmhen bit is set to 1, 8-bit timer hn starts c ounting. the carrier clock is maintained inactive at this time. <3> when the count value of 8-bit timer counter hn and th e set value of the cmpn0 r egister match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register t hat is compared with 8-bit timer counter hn changes from the cm pn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is invert ed, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a fixed duty (other than 50%) is generated through the repetiti on of steps <3> and <4>. <5> the inttm5n signal is generated. this signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the carrier is output from the rising edge of t he first carrier clock by setting the nrzn bit = 1. <7> by setting the nrzn bit = 0, the tohn output is also main tained high level while the carrier clock is high level, and does not change to low level (the high level width of the carrier waveform is guaranteed through steps <6> and <7>). remark n = 0, 1
chapter 9 8-bit timer h preliminary user?s manual u16892ej1v0ud 302 figure 9-8. carrier ge nerator mode (3/3) operation based on cmpn1 transitions 8-bit timer hn count clock cmpn0 tmhen inttmhn carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>' <4> <3> <2> cmpn1 <5> m n l m (l) 8-bit timer counter hn count value <1> when the tmhen bit is set to 1, counting starts. the carrier clock is maintained inactive at this time. <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, 8-bit timer counter hn is cleared to 00h and the inttmhn signal is output. <3> the cmpn1 register can be rewri tten during 8-bit timer hn operation, but the changed value (l) is latched. the value of the cmpn1 register is changed when the co unt value of 8-bit timer counter hn and the value of the cmpn1 register prior to the change (m) match (<3>?). <4> when the count value of 8-bit timer counter hn and the value (m) of the cmpn1 re gister match, the inttmhn signal is output, the carrier signal is inverted, and 8-bit timer counter hn is cleared to 00h. <5> the timing at which the count value of 8-bit timer counter hn and the value of the cmpn1 register match again is the changed value (l). remark n = 0, 1
preliminary user?s manual u16892ej1v0ud 303 chapter 10 interval timer, watch timer the v850es/ke1 includes interval timer brg and a watch ti mer. interval timer brg can also be used as the source clock of the watch timer. the watch timer can also be used as interval timer wt. two interval timer channels and one watch timer channel can be used at the same time. 10.1 interval timer brg 10.1.1 functions interval timer brg has the following functions. ? ?
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 304 (1) clock control the clock control controls supp ly/stop of the operation clock (f x ) of interval timer brg. (2) 3-bit prescaler the 3-bit prescaler divides f x to generate f x /2, f x /4, and f x /8. (3) selector the selector selects the count clock (f bgcs ) for interval timer brg from f x , f x /2, f x /4, and f x /8. (4) 8-bit counter the 8-bit counter counts the count clock (f bgcs ). (5) output control the output control controls supply of the count clock (f brg ) for the watch timer. (6) prscm register the prscm register is an 8-bit compare re gister that sets the interval time. (7) prsm register the prsm register controls the oper ation of interval timer brg, the selector, and clock supply to the watch timer.
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 305 10.1.3 registers interval timer brg includes the following registers. (1) interval timer brg mode register (prsm) prsm controls the operation of interval timer brg, se lection of count clock, and clock supply to the watch timer. this register can be read or written in 8-bit or 1-bit units. after reset, prsm is cleared to 00h. 0 prsm 0 0 bgce 0 todis bgcs1 bgcs0 operation stopped, 8-bit counter cleared to 01h operate bgce 0 1 control of interval timer operation f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs1 0 0 1 1 bgcs0 0 1 0 1 selection of input clock (f bgcs ) note after reset: 00h r/w address: fffff8b0h clock for watch timer supplied clock for watch timer not supplied todis 0 1 control of clock supply for watch timer 10 mhz 100 ns 200 ns 400 ns 800 ns < > note set these bits so that the fo llowing conditions are satisfied. v dd = 4.0 to 5.5 v: f bgcs 10 mhz v dd = 2.7 to 4.0 v: f bgcs 5 mhz cautions 1. do not change the values of the todi s, bgcs1, and bgcs0 bits while interval timer brg is operating (bgce bit = 1). set the todis, bgcs1, and bgcs0 bits before setting (1) the bgce bit. 2. when the bgce bit is clea red (to 0), the 8-bit counter is cleared.
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 306 (2) interval timer brg compare register (prscm) prscm is an 8-bit compare register. this register can be read or written in 8-bit units. after reset, prscm is cleared to 00h. prscm7 prscm prscm6 prscm5 prscm4 prscm3 prscm2 prscm1 prscm0 after reset: 00h r/w address: fffff8b1h caution do not rewrite the prscm regi ster while interval timer brg is operating (prsm.bgce bit = 1). set the prscm register before setting (1) the bgce bit.
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 307 10.1.4 operation (1) operation of interval timer brg set the count clock by using the prsm.bgcs1 and prsm .bgcs0 bits and the 8-bit compare value by using the prscm register. when the prsm.bgce bit is set (1), interval timer brg starts operating. each time the count value of the 8-bit counter and the set value in the prscm register match, an interrupt request signal (intbrg) is generated. at the same time, the 8-bit counter is cleared to 00h and counting is continued. the interval time can be obtained from the following equation. interval time = 2 m n/f x remark m: divided value (set value in the bgcs1 and bgcs0 bits) = 0 to 3 n: set value in prscm register = 1 to 256 (when the set value in the prscm register is 00h, n = 256) f x : main clock oscillation frequency (2) count clock supply for watch timer set the count clock by using the prsm.bgcs1 and prsm .bgcs0 bits and the 8-bit compare value by using the prscm register, so that the count clock frequency (f brg ) of the watch timer is 32.768 khz. clear (0) the prsm.todis bit at the same time. when the prsm.bgce bit is set (1), f brg is supplied to the watch timer. f brg is obtained from the following equation. f brg = f x /(2 m+ 1 n) to set f brg to 32.768 khz, perform the following calculat ion to set the bgcs1 and bgcs0 bits and the prscm register. <1> set n = f x /65,536 (round off the decimal) to set m = 0. <2> if n is even, n = n/2 and m = m + 1 <3> repeat step <2> until n is odd or m = 3 <4> set n to the prscm register and m to the bgcs1 and bgcs0 bits. example: when f x = 4.00 mhz <1> n = 4,000,000/65,536 = 61 (r ound off the decimal), m = 0 <2>, <3> since n is odd, the values remain as n = 61, m = 0 <4> the set value in the prscm register: 3 dh (61), the set values in the bgcs1 and bgcs0 bits: 00 remark m: divided value (set value in the bgcs1 and bgcs0 bits) = 0 to 3 n: set value in prscm register = 1 to 256 (when the set value in the prscm register is 00h, n = 256) f x : main clock oscillation frequency
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 308 10.2 watch timer 10.2.1 functions the watch timer has the following functions. ? ?
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 309 (1) 11-bit prescaler the 11-bit prescaler generates a clock of f w /2 4 to f w /2 11 by dividing f w . (2) 5-bit counter the 5-bit counter generates the watch timer interru pt request signal (intwt) at intervals of 2 4 /f w , 2 5 /f w , 2 13 /f w , or 2 14 /f w by counting f w or f w /2 9 . (3) selectors the watch timer has the following four selectors. ? ? ? ?
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 310 wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.91 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.3 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval time of prescaler wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < >
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 311 10.2.4 operation (1) operation as watch timer the watch timer generates an interrupt re quest at fixed time intervals. the watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 khz). the count operation starts when the wtm.wtm0 and wtm. wtm1 bits are set to 11. when these bits are cleared to 00, the 11-bit prescaler and 5-bit count er are cleared and the count operation stops. the 5-bit counter can be cleared to synchronize the time by clearing the wtm1 bit to 0 when the watch timer and interval timer wt operate simultaneously. at this ti me, an error of up to 15.6 ms may occur in the watch timer, but interval timer wt is not affected. (2) operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (intwti) at intervals specified by a count value set in advance. the interval time can be selected by the wtm.wtm4 to wtm.wtm7 bits. table 10-1. interval ti me of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 312 figure 10-3. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remarks 1. assuming that the interrupt time of the watch timer is set to 0.5 seconds. 2. f w : watch timer clock frequency values in parentheses apply when count clock f w = 32.768 khz. n: number of interval timer wt operations 10.3 cautions (1) operation as watch timer some time is required before the first watch timer in terrupt request (intwt) is generated after operation is enabled (wtm.wtm1 and wtm.wtm0 bits = 11). figure 10-4. example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) it takes 0.515625 (max.) seconds for the first intwt to be generated (2 9
chapter 10 interval timer, watch timer preliminary user?s manual u16892ej1v0ud 313 (2) when watch timer and interval timer brg operate simultaneously when using the subclock as the count clock for the watch ti mer, the interval time of interval timer brg can be set to any value. changing the interval time does not a ffect the watch timer (before changing the interval time, stop operation). when using the main clock as the count clock for the watch timer, set the interval time of interval timer brg to approximately 65,536 hz. do not change this value. (3) when interval timer brg and inter val timer wt operate simultaneously when using the subclock as the count clock for interval ti mer wt, the interval times of interval timers brg and wt can be set to any values. they can also be cha nged later (before changing the value, stop operation). when using the main clock as the count clock for interval timer wt, the interval time of interval timer brg can be set to any value, but cannot be changed later (it can be changed only when interval timer wt stops operation). the interval time of interval timer wt can be set to
preliminary user?s manual u16892ej1v0ud 314 chapter 11 watchdog timer functions 11.1 watchdog timer 1 11.1.1 functions watchdog timer 1 has the following operation modes. ? ? ? ? ?
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 315 figure 11-1. block diagra m of watchdog timer 1 wdtm14 wdtm13 run1 2 intwdtm1 wdtres1 3 wdcs1 wdcs0 wdcs2 f xw /2 21 f xw /2 15 f xw /2 16 f xw /2 17 f xw /2 18 f xw /2 19 f xw /2 14 f xw /2 13 intwdt1 f xw internal bus watchdog timer mode register 1 (wdtm1) watchdog timer clock selection register (wdcs) output controller prescaler clear selector remark intwdtm1: request signal for maskable interrupt through watchdog timer 1 overflow intwdt1: request signal for non-maskable inte rrupt through watchdog timer 1 overflow wdtres1: reset signal through watchdog timer 1 overflow f xw = f x : watchdog timer 1 clock frequency
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 316 11.1.2 configuration watchdog timer 1 consists of the following hardware. table 11-1. configuration of watchdog timer 1 item configuration control registers watchdog timer clock select ion register (wdcs) watchdog timer mode register 1 (wdtm1) 11.1.3 registers the registers that control watchdo g timer 1 are as follows. ? ?
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 317 (2) watchdog timer mode register 1 (wdtm1) this register sets the watchdog timer 1 operati on mode and enables/disables count operations. this register is a special register that c an be written only in a special sequence (refer to 3.4.7 special registers ). the wdtm1 register can be read or written in 8-bit or 1-bit units. after reset, wdtm1 is cleared to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm1 register using an access method that causes a wait. for details, refer to 3.4.8 (2). run1 stop counting clear counter and start counting run1 0 1 selection of operation mode of watchdog timer 1 note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (upon overflow, maskable interrupt intwdtm1 is generated.) watchdog timer mode 1 note 3 (upon overflow, non-maskable interrupt intwdt1 is generated.) watchdog timer mode 2 (upon overflow, reset operation wdtres1 is started.) wdtm14 0 0 1 1 wdtm13 0 1 0 1 selection of operation mode of watchdog timer 1 note 2 < > notes 1. once the run1 bit is set (to 1), it c annot be cleared (to 0) by software. therefore, when counti ng is started, it cannot be stopped except by reset. 2. once the wdtm13 and wdtm14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only by reset. 3. for non-maskable interrupt servicing due to non -maskable interrupt request signal (intwdt1), refer to 17.10 cautions .
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 318 11.1.4 operation (1) operation as watchdog timer 1 watchdog timer 1 operation to detect a program loop is selected by setting the wdtm1.wdtm14 bit to 1. the count clock (program loop detection time interv al) of watchdog timer 1 can be selected using the wdcs.wdcs0 to wdcs.wdcs2 bits. the count operation is started by setting the wdtm1.run1 bit to 1. when, after the count operation is st arted, the run1 bit is again set to 1 within the set program loop detection time interval, watchdog timer 1 is cleared and the count operation starts again. if the program loop detection time is exceeded without run1 bit being set to 1, reset signal (wdtres1) through the value of the wdtm1.wdtm13 bit or a non-maskable interrupt request signal (intwdt1) is generated. the count operation of watchdog timer 1 stops in t he stop mode and idle mode. set the run1 bit to 1 before the stop mode or idle mode is entered in order to clear watchdog timer 1. because watchdog timer 1 operates in the halt mode, make sure that an overflow will not occur during halt. cautions 1. when the subclock is selected for the cpu cl ock, the count operation of watchdog timer 1 is stopped (the value of watc hdog timer 1 is maintained). 2. for non-maskable interrupt servicing due to the intwdt1 signal, refer to 17.10 cautions. table 11-2. program loop detect ion time of watchdog timer 1 program loop detection time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.277 ms 1.683 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 319 (2) operation as interval timer watchdog timer 1 can be made to operate as an interval ti mer that repeatedly generates interrupts using the count value set in advance as the interval, by clearing the wdtm1.wdtm14 bit to 0. when watchdog timer 1 operates as an interval time r, the interrupt mask flag (wdtmk) and priority specification flags (wdtpr0 to wdtpr2) of the wdti c register are valid and maskable interrupt request signals (intwdtm1) can be generated. the default priority of the intwdtm1 signal is set to the highest level among the maskable interrupt request signals. the interval timer continues to operate in the halt mode, but it stops operating in the stop mode and the idle mode. cautions 1. once the wdtm14 bit is set to 1 (thereby selecting the watc hdog timer 1 mode), the interval timer mode is not entered as long as reset is not performed. 2. when the subclock is sel ected for the cpu clock, the count operation of the watchdog timer 1 stops (the value of the wa tchdog timer is maintained). table 11-3. interval ti me of interval timer interval time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.277 ms 1.638 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 320 11.2 watchdog timer 2 11.2.1 functions watchdog timer 2 has the following functions. ? ?
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 321 11.2.2 configuration watchdog timer 2 consists of the following hardware. table 11-4. configuration of watchdog timer 2 item configuration control registers watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) 11.2.3 registers (1) watchdog timer mode register 2 (wdtm2) this register sets the overflow time and operation clock of watchdog timer 2. the wdtm2 register can be read or writt en in 8-bit units. this register c an be read any number of times, but it can be written only once following reset release. after reset, wdtm2 is set to 67h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm2 register using an access method that causes a wait. for details, refer to 3.4.8 (2). 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2) reset mode (generation of wdtres2) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. to stop the operation of watchdog ti mer 2, write ?1fh? to the wdtm2 register. 2. for details about bits wdcs0 to wdcs4, refer to table 11-5 watchdog timer 2 clock selection. 3. if the wdtm2 register is written twice afte r a reset, an overflow signal is forcibly output.
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 322 table 11-5. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 0 0 2 18 /f xx 13.1 ms 16.4 ms 26.2 ms 0 0 0 0 1 2 19 /f xx 26.2 ms 32.8 ms 52.4 ms 0 0 0 1 0 2 20 /f xx 52.4 ms 65.5 ms 104.9 ms 0 0 0 1 1 2 21 /f xx 104.9 ms 131.1 ms 209.7 ms 0 0 1 0 0 2 22 /f xx 209.7 ms 262.1 ms 419.4 ms 0 0 1 0 1 2 23 /f xx 419.4 ms 524.3 ms 838.9 ms 0 0 1 1 0 2 24 /f xx 838.9 ms 1048.6 ms 1677.7 ms 0 0 1 1 1 2 25 /f xx 1677.7 ms 2097.2 ms 3355.4 ms 0 1 0 0 0 2 9 /f xt 15.625 ms (f xt = 32.768 khz) 0 1 0 0 1 2 10 /f xt 31.25 ms (f xt = 32.768 khz) 0 1 0 1 0 2 11 /f xt 62.5 ms (f xt = 32.768 khz) 0 1 0 1 1 2 12 /f xt 125 ms (f xt = 32.768 khz) 0 1 1 0 0 2 13 /f xt 250 ms (f xt = 32.768 khz) 0 1 1 0 1 2 14 /f xt 500 ms (f xt = 32.768 khz) 0 1 1 1 0 2 15 /f xt 1000 ms (f xt = 32.768 khz) 0 1 1 1 1 2 16 /f xt 2000 ms (f xt = 32.768 khz) 1
chapter 11 watchdog timer functions preliminary user?s manual u16892ej1v0ud 323 11.2.4 operation watchdog timer 2 automatically starts in t he reset mode following reset release. the wdtm2 register can be written to only once following reset through byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm 2 register using 8-bit memory manipulation instructions. after this is done, the operation of watchdog timer 2 cannot be stopped. the watchdog timer 2 program loop detection time in terval can be selected by the wdtm2.wdcs24 to wdtm2.wdcs20 bits. writing ach to the wdte register clears the counter of watchdog timer 2 and starts the count operation again. after the count operat ion starts, write ach to the wdte r egister within the set program loop detection time interval. if the program loop detection time is exceeded without a ch being written to the wdte register, a reset signal (wdtres2) or non-maskable interrupt request signal (i ntwdt2) is generated depending on the set value of the wdtm2.wdm21 and wdtm2.wdm20 bits. to not use watchdog timer 2, writ e 1fh to the wdtm2 register. for non-maskable interrupt servicing when the non -maskable interrupt request mode is set, refer to 17.10 cautions . if the main clock is selected as the source clock of wa tchdog timer 2, the watchdog timer stops operation in the idle/stop mode. therefore, clear wa tchdog timer 2 by writing ach to the wdte register before the idle/stop mode is set. because watchdog timer 2 operates in the halt mode or w hen the subclock is selected as its source clock in the idle/stop mode, exercise care that the ti mer does not overflow in the halt mode.
preliminary user?s manual u16892ej1v0ud 324 chapter 12 real-time output function (rto) 12.1 function the real-time output function (rto) transfers preset data to the rtbl0 and rtbh0 registers, and then transfers this data with hardware to an external device via the r eal-time output latches, upon occurr ence of a timer interrupt. the pins through which the data is output to an external device constitute a port called a real-time output port. because rto can output signal without jitter, it is suitable for controlling a stepping motor. in the v850es/ke1, a 6-bit real-time output port channel is provided. the real-time output port can be se t in the port mode or real-time output port mode in 1-bit units. the block diagram of rto is shown below. figure 12-1. block diagram of rto real-time buffer register 0h (rtbh0) real-time output latch 0h selector inttm50 inttm51 real-time output latch 0l rtpoe0 rtpeg0 byte0 extr0 real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 real-time output port mode register 0 (rtpm0) 4 2 2 4 internal bus real-time buffer register 0l (rtbl0) rtpout04, rtpout05 rtpout00 to rtpout03
chapter 12 real-time output function (rto) preliminary user?s manual u16892ej1v0ud 325 12.2 configuration rto consists of the following hardware. table 12-1. configuration of rto item configuration registers real-time output buffe r register 0 (rtbl0, rtbh0) control registers real-time output port mode register 0 (rtpm0) real-time output port control register 0 (rtpc0) (1) real-time output buffer register 0 (rtbl0, rtbh0) rtbl0 and rtbh0 are 4-bit registers t hat hold output data in advance. these registers are mapped to independent addresses in the peripheral i/o register area. they can be read or written in 8-bit or 1-bit units. if an operation mode of 4 bits
chapter 12 real-time output function (rto) preliminary user?s manual u16892ej1v0ud 326 12.3 registers rto is controlled using the foll owing two types of registers. ? ?
chapter 12 real-time output function (rto) preliminary user?s manual u16892ej1v0ud 327 (2) real-time output port control register 0 (rtpc0) this register sets the operation mode and ou tput trigger of the real-time output port. the relationship between the operation mo de and output trigger of the real -time output port is as shown in table 12-3. the rtpc0 register can be read or written in 8-bit or 1-bit units. after reset, rtpc0 is cleared to 00h. rtpoe0 disables operation note 3 enables operation rtpoe0 0 1 control of real-time output operation rtpc0 rtpeg0 note 1 byte0 extr0 note 2 00 0 0 4 bits
chapter 12 real-time output function (rto) preliminary user?s manual u16892ej1v0ud 328 12.4 operation if the real-time output operation is enabled by setting the rtpc0.rtpoe0 bi t to 1, the data of the rtbh0 and rtbl0 registers is transferred to the real-time output latch in synchronizati on with the generation of the selected transfer trigger (set by the rtpc0.extr0 and rtpc0.byte0 bits). of the trans ferred data, only the data of the bits specified as real-time output enabled by the rtpm0 register is output from bi ts rtpout00 to rtpo ut05. the bits specified as real-time output disabled by the rtpm0 register output 0. if the real-time output operatio n is disabled by clearing the rtpoe0 bi t to 0, the rtpout00 to rtpout05 signals output 0 regardless of the setti ng of the rtpm0 register. figure 12-2. example of operation timing (when extr0 and byte0 bits = 00) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttm51 (internal) inttm50 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by inttm51 interrupt request signal (write to rtbh0 register) b: software processing by inttm50 interrupt request signal (write to rtbl0 register) remark for the operation during standby, refer to chapter 19 standby function .
chapter 12 real-time output function (rto) preliminary user?s manual u16892ej1v0ud 329 12.5 usage (1) disable real-time output. clear the rtpc0.rtpoe0 bit to 0. (2) perform initializa tion as follows. ? ? ? ? ?
chapter 12 real-time output function (rto) preliminary user?s manual u16892ej1v0ud 330 12.7 security function a circuit that sets the pin outputs to high impedance as a security functi on for when malfunctions of a stepping motor controlled by rto occur is provided on chip. it fo rcibly resets the pins allocated to rtp00 to rtp05 via external interrupt intp0 pin edge detection, placing them in t he high-impedance state. the ports (p50 to p55 pins) placed in high impedance by intp0 note 1 pin are initialized note 2 , so settings for these ports must be performed again. notes 1. regardless of the port settings, p50 to p55 pins are all placed in high impedance via the intp0 pin. 2. the bits that are initialized are a ll the bits corresponding to p50 to p 55 pins of the following registers. ? p5 register ? pm5 register ? pmc5 register ? pu5 register ? pfc5 register the block diagram of the security function is shown below. figure 12-3. block diagra m of security function edge detection intc intp0 rtost0 rtpout00 to rtpout05 rtp00 to rtp05 ev dd r 6 this function is set with the pllctl.rtost0 bit.
chapter 12 real-time output function (rto) preliminary user?s manual u16892ej1v0ud 331 (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the rto security function and pll. this register can be read or writt en in 8-bit or 1-bit units. after reset, pllctl is set to 01h. 0 pllctl 0 0 0 0 rtost0 selpll note pllon note intp0 pin is not used as trigger for security function intp0 pin is used as trigger for security function rtost0 0 1 control of rtp00 to rtp05 security function after reset: 01h r/w address: fffff806h < > < > < > note for details on the selpll and pllon bits, refer to chapter 5 clock generation function . cautions 1. before outputting a value to the real-time output po rts (rtp00 to rtp05), select the intp0 pin interrupt edge det ection and then set the rtost0 bit. 2. to set again the ports (p50 to p 55 pins) as real-time output ports after placing them in high impedance via th e intp0 pin, first cancel the security function. [procedure to set ports again] <1> cancel the security function and enable port setting by clearing the rtost0 bit to 0. <2> set the rtost0 bit to 1 (only if required). <3> set again as real-time output port. 3. be sure to clear bits 4 to 7 to 0. changing bit 3 does not affect the operation.
preliminary user?s manual u16892ej1v0ud 332 chapter 13 a/d converter 13.1 functions the a/d converter converts analog input signals into digita l values with a resolution of 10 bits and has an 8- channel (ani0 to ani7) configuration. the a/d converter has the following functions. (1) 10-bit resolution a/d conversion 1 analog input channel is selected from ani0 to ani7 , and an a/d conversion operation with resolution of 10 bits is repeatedly executed. every time a/d conversion is completed, an interrupt request signal (intad) is generated. (2) power fail detection function this is a function to detect low voltage in a battery. the results of a/d conversi on (the value in the adcrh register) and the pft register are compared, and in tad signal is generated only when the comparison conditions match.
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 333 13.2 configuration the a/d converter consists of the following hardware. figure 13-1. block diag ram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 av ref0 av ss intad adcs bit 3 ads2 ads1 ads0 adcs fr2 fr1 adcs2 fr0 sample & hold circuit av ss voltage comparator controller a/d conversion result register (adcr/adcrh) power fail comparison threshold register (pft) analog input channel specification register (ads) a/d converter mode register (adm) pfen pfcm power fail comparison mode register (pfm) internal bus successive approximation register (sar) comparator tap selector selector table 13-1. registers of a/ d converter used by software item configuration registers a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read power fail comparison threshold register (pft) a/d converter mode register (adm) analog input channel specification register (ads) power fail comparison mode register (pfm)
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 334 (1) ani0 to ani7 pins these are analog input pins for the 8 channels of the a/ d converter. they are used to input analog signals to be converted into digital signals. pins other than thos e selected as analog input by the ads register can be used as input ports. (2) sample & hold circuit the sample & hold circuit samples the analog input si gnals selected by the input circuit and sends the sampled data to the voltage comparator. this ci rcuit holds the sampled analog input voltage during a/d conversion. (3) series resistor string the series resistor string is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (4) voltage comparator the voltage comparator com pares the value that is sampled and hel d with the output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage value with the voltage value from the series resistor string, and converts the comparison result starti ng from the most significant bit (msb). when the least significant bit (lsb) has been converted to a digital value (end of a/d conversion), the contents of the sar register are transfe rred to the adcr register. the sar register cannot be read or written directly. (6) a/d conversion result register (adcr) , a/d conversion result register h (adcrh) each time a/d conversion ends, the conversion results are loaded from the successive approximation register and the results of a/d conversion are held in the higher 10 bits of this regist er (the lower 6 bits are fixed to 0). (7) controller the controller compares the a/d c onversion results (the value of the adcrh register) with the value of the pft register when a/d conversion ends or the power fail detection function is used. it generates intad signal only when the comparison conditions match. (8) av ref0 pin this is the analog power supply pin/reference voltage input pin of the a/d converter. always use the same potential as the v dd pin even when not using the a/d converter. the signals input to the ani0 to ani7 pins are conv erted into digital signals based on the voltage applied across av ref0 and av ss . (9) av ss pin this is the ground potential pin of the a/d converter. always use the same potential as the v ss pin even when not using the a/d converter.
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 335 (10) a/d converter mode register (adm) this register sets the conversion time of the analog input to be converted to a digital signal and the conversion operation start/stop. (11) analog input channel sp ecification register (ads) this register specifies the input port for the analog voltage to be converted to a digital signal. (12) power fail comparis on mode register (pfm) this register sets the power fail monitoring mode. (13) power fail comparison threshold register (pft) this register sets the threshold to be compared with the adcr register. 13.3 registers the a/d converter is controlle d by the following registers. ? ? ? ? ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 336 (1) a/d converter mode register (adm) this register sets the conversion time of the analog input signal to be convert ed into a digital signal as well as conversion start and stop. the adm register can be read or wr itten in 8-bit or 1-bit units. after reset, adm is cleared to 00h. adcs adcs 0 1 conversion operation stopped conversion operation enabled control of a/d conversion operation adm 0 fr2 fr1 fr0 0 0 adcs2 after reset: 00h r/w address: fffff200h fr2 0 0 0 0 1 1 1 1 fr1 0 0 1 1 0 0 1 1 fr0 0 1 0 1 0 1 0 1 288/f xx 240/f xx 192/f xx setting prohibited 144/f xx 120/f xx 96/f xx setting prohibited 14.4 s setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited 18.0 s 15.0 s setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited conversion time note 1 selection of conversion time 20 mhz 16 mhz 28.8 s 24.0 s 19.2 s setting prohibited 14.4 s setting prohibited setting prohibited setting prohibited 10 mhz f xx adcs2 0 1 reference voltage generator operation stopped reference voltage generator operation enabled control of reference voltage generator for boosting operation note 2 < > < >
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 337 table 13-2. setting of adcs bit and adcs2 bit adcs adcs2 a/d co nversion operation 0 0 stopped status (dc power consumption path does not exist) 0 1 conversion standby mode (only the refer ence voltage generator for boosting consumes power) 1 0 conversion mode (reference voltage generator stops operation note ) 1 1 conversion mode (reference voltage generator is operating) note the data obtained by the firs t conversion must not be used. figure 13-2. operation sequence comparator control conversion operation conversion standby conversion operation conversion stop adcs adcs2 note reference voltage generator for boosting: operating note 17
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 338 (2) analog input channel specification register (ads) this register specifies the analog vo ltage input port for a/d conversion. the ads register can be read or written in 8-bit units. after reset, ads is cleared to 00h. 0 ads 0 0 0 0 ads2 ads1 ads0 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads2 0 0 0 0 1 1 1 1 ads1 0 0 1 1 0 0 1 1 ads0 0 1 0 1 0 1 0 1 specification of analog input channel after reset: 00h r/w address: fffff201h cautions 1. be sure to clear bits 3 to 7 to 0. 2. when the main clock is stopped and the cpu is operating on the subclock, do not access the ads re gister using an access method that causes a wait. for details, refer to 3.4.8 (2).
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 339 (3) a/d conversion result register, a/d conversion result register h (adcr, adcrh) the adcr and adcrh registers stor e the a/d conversion results. these registers are read-only in 16-bit or 8-bit units. however, specify the adcr register for 16-bit access, and the adcrh register for 8-bit access. in the adcr r egister, the 10 bits of conversion results are read in the higher 10 bits and 0 is read in the lower 6 bits. in the adcrh register, the higher 8 bits of the conversion results are read. after reset, these registers are undefined. after reset: undefined r address: fffff204h adcr ad9 ad8 ad7 ad6 ad0 0 0 0 0 0 0 ad1 ad2 ad3 ad4 ad5 ad9 adcrh ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: fffff205h caution when the main clock is st opped and the cpu is operating on the subclock, do not access the adcr and adcrh registers using an access method that causes a wait. fo r details, refer to 3.4.8 (2).
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 340 the following shows the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and a/d conversion results (adcr register). sar = int ( ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 341 (4) power fail comparison mode register (pfm) this register sets the power fail monitoring mode. the pfm register compares the value in the p ft register with the val ue of the adcrh register. the pfm register can be read or wr itten in 8-bit or 1-bit units. after reset, pfm is cleared to 00h. pfen pfen 0 1 power fail comparison disabled power fail comparison enabled selection of power fail comparison enable/disable pfm pfcm 0 0 0 0 0 0 pfcm 0 1 interrupt request signal (intad) generated when adcr
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 342 13.4 operation 13.4.1 basic operation <1> select the channel whose analog signal is to be c onverted into a digital signal using the ads register. <2> set (1) the adm.adcs2 bit and wait 17 ? ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 343 13.4.2 a/d conversion operation ? ? ? ? ? ? ? ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 344 the following describes how to set registers. ? ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 345 13.5 cautions (1) power consumpti on in standby mode the operation of the a/d converter st ops in the standby mode. at this time, the power consumption can be reduced by stopping the conversion operation (the adm.adcs bit = 0). figure 13-5 shows an example of how to reduce the power consumpti on in the standby mode. figure 13-5. example of how to redu ce power consumption in standby mode adcs series resistor string av ref0 p-ch av ss (2) input range of ani0 to ani7 pins use the a/d converter with the ani0 to ani7 pin input voltages within the specified range. if a voltage of av ref0 or higher or av ss or lower (even if within the absolute maxi mum ratings) is input to these pins, the conversion value of the channel is undefined. also, this may affect the conversion value of other channels. (3) conflicting operations (a) conflict between writing to t he adcr register and reading from adcr register upon the end of conversion reading the adcr register takes precedence. after the register has been read, a new conversion result is written to the adcr register. (b) conflict between writing to the adcr register and writing to the adm register or writing to the ads register upon the end of conversion writing to the adm register or ads register takes precedence. the adcr regist er is not written, and neither is the conversion end interr upt request signal (intad) generated.
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 346 (4) measures against noise to keep a resolution of 10 bits, be aware of noise on the av ref0 and ani0 to ani7 pins. the higher the output impedance of the analog input source, the greater the effect of noise. therefore, it is recommended to connect external capacitors as shown in figure 13-6 to reduce noise. figure 13-6. handling of analog input pins av ref0 ani0 to ani7 av ss v ss if noise of av ref0 or higher or av ss or lower could be generated, clamp with a diode with a small v f (0.3 v or lower). reference voltage input c = 100 to 1000 pf (5) ani0/p70 to ani7/p77 pins the analog input pins (ani0 to ani7) function alternately as input port pins (p70 to p77). when performing a/d conversion by selecting any of th e ani0 to ani7 pins, do not execute an input instruction to port 7 during conversion. th is may decrease the conversion resolution. if digital pulses are applied to the pin adjacent to the pin subject to a/d conversi on, the value of the a/d conversion may differ from the expected value because of coupling noise. therefore, do not apply pulses to the pin adjacent to the pin subject to a/d conversion. (6) input impedance of av ref0 pin a series resistor string of tens of k ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 347 (7) interrupt request flag (adic.adif bit) even when the ads register is changed, the adif bit is not cleared (0). therefore, if the analog input pin is changed during a/d conversion, the adif bit may be set (1) because a/d conversion of the previous analog input pin ends immediately before the ads register is rewritten. in a such case, note that if the adif bit is r ead immediately after the ads register ha s been rewritten, the adif bit is set (1) even though a/d conversion of the analog in put pin after the change has not been completed. when stopping a/d conversion once and resuming it, clea r the adif bit (0) before resuming a/d conversion. figure 13-7. a/d conversion end in terrupt request occurrence timing anin anin anin anim anim anin anim anim a/d conversion adcr intad ads rewrite (anin conversion start) ads rewrite (anim conversion start) anim conversion is not complete even though adif is set. remark n = 0 to 7 m = 0 to 7 (8) conversion results immediat ely after a/d conversion start if the adm.adcs bit is set to 1 within 17
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 348 (10) a/d converter sampling time a nd a/d conversion start delay time the a/d converter sampling time differs depending on the se t value of the adm register. a delay time exists until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 13-8 and table 13-3. figure 13-8. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time conversion time a/d conversion start delay time sampling time sampling timing intad adcs ? ? ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 349 (11) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 13-9. internal equivalent circuit of anin pin anin c out c in r in av ref0 r in c out c in 4.5 v 3 k ? ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 350 13.6 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltag e that can be identified. that is , the percentage of the analog input voltage per bit of digital output is called 1 lsb (least si gnificant bit). the percent age of 1 lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always r epresented by the following formula regardless of the resolution. 1 %fsr = (max. value of analog in put voltage that can be converted ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 351 (3) quantization error when analog values are converted to digital values, a
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 352 (5) full-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (full scale ?
chapter 13 a/d converter preliminary user?s manual u16892ej1v0ud 353 (7) integral linearity error this shows the degree to which the conversion characterist ics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measur ement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 13-15. integral linearity error 0 av ref0 digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when the analog input vo ltage was applied to the time when the digital output was obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 13-16. sampling time sampling time conversion time
preliminary user?s manual u16892ej1v0ud 354 chapter 14 asynchronous serial interface (uart) in the v850es/ke1, two channels of asynchronous serial interface (uart) are provided. 14.1 features ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 355 14.2 configuration table 14-1. configuration of uartn item configuration registers receive buffer register n (rxbn) transmit buffer register n (txbn) receive shift register transmit shift register asynchronous serial interface mode register n (asimn) asynchronous serial interface status register n (asisn) asynchronous serial interface tran smit status register n (asifn) other reception control parity check addition of transmissi on control parity remark n = 0, 1 figure 14-1 shows the configuration of uartn. (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register for specifying the operation of uartn. (2) asynchronous serial interfa ce status register n (asisn) the asisn register consists of a set of flags that indicate the erro r contents when a reception error occurs. the various reception error flags are set (1) when a reception error occurs and are cleared (0) when the asisn register is read. (3) asynchronous serial interface tran smit status register n (asifn) the asifn register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, which indicates the hol d status of the t xbn register data, and the transmit shift register data flag, which indicates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the c ontents set in the asimn register. a check for parity errors is also performed during a re ceive operation, and if an error is detected, a value corresponding to the error contents is set in the asisn register. (5) receive shift register this is a shift register that converts the serial data t hat was input to the rxdn pin to parallel data. one byte of data is received, and if a stop bi t is detected, the receive data is transferred to the rxbn register. this register cannot be directly manipulated. (6) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for holdi ng receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, re ceive data is transferred from the re ceive shift register to the rxbn register, synchronized with the end of t he shift-in processing of one frame. also, the reception completion interrupt request signal (intsrn) is generated by t he transfer of data to the rxbn register.
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 356 (7) transmit shift register this is a shift register that converts the parallel data that was transferred from the txbn register to serial data. when one byte of data is transferred fr om the txbn register, the shift regi ster data is output from the txdn pin. the transmission completion interrupt request signal (int stn) is generated synchronized with the completion of transmission of one frame. this register cannot be directly manipulated. (8) transmit buffer register n (txbn) the txbn register is an 8-bit buffer for transmit data. a transmit operation is star ted by writing transmit data to the txbn register. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, par ity bit, or stop bit to the data that is written to the txbn register, according to the contents that were set in the asimn register. figure 14-1. block diagram of uartn parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer register n (rxbn) receive shift register reception control parity check transmit buffer register n (txbn) transmit shift register addition of transmission control parity baud rate generator n intsren intsrn intstn rxdn txdn remark for the configuration of the baud rate generator, refer to figure 14-12 .
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 357 14.3 registers (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register t hat controls the uartn transfer operation. this register can be read or written in 8-bit or 1-bit units. after reset, asimn is set to 01h. cautions 1. when using uartn, be sure to set th e external pins related to uartn functions to the control mode before setting the cksrn and brgcn registers, and then set the uarten bit to 1. then set the other bits. 2. set the uarten and rxen bits to 1 while a high level is input to the rxdn pin. if these bits are set to 1 while a low level is input to the rxdn pin, reception will be started. (1/2) <7> uarten asimn (n = 0, 1) <6> txen <5> rxen 4 psn1 3 psn0 2 cln 1 sln 0 isrmn after reset: 01h r/w address: asim0 fffffa00h, asim1 fffffa10h uarten control of operating clock 0 stop clock supply to uartn. 1 supply clock to uartn. ? ? ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 358 (2/2) rxen reception enable/disable 0 disable reception note 1 enable reception ? ? ? ? ? ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 359 (2) asynchronous serial interfa ce status register n (asisn) the asisn register, which consists of 3 error flag bits (pen, fen, and oven), indicates the error status when uartn reception is complete. the asisn register is cleared to 00h by a read operation. when a recept ion error occurs, the rxbn register should be read and the error flag should be cl eared after the asisn register is read. this register is read-only in 8-bit units. after reset, asisn is cleared to 00h. cautions 1. when the asimn.uarten bit or asimn. rxen bit is cleared to 0, or when the asisn register is read, the pen, fen, and oven bits are cleared (0). 2. operation using a bit manipula tion instruction is prohibited. 3. when the main clock is stopped and th e cpu is operating on the subclock, do not access the asisn register using an access method that causes a wait. for details, refer to 3.4.8 (2). 7 0 asisn (n = 0, 1) 6 0 5 0 4 0 3 0 2 pen 1 fen 0 oven after reset: 00h r address: asis0 fffffa03h, asis1 fffffa13h pen status flag indicating a parity error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read 1 when reception was completed, the receive data parity did not match the parity bit ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 360 (3) asynchronous serial interface tran smit status register n (asifn) the asifn register, which consists of 2 status flag bits, indicates the status during transmission. by writing the next data to the txbn register after data is transferred from the txbn register to the transmit shift register, transmit operations can be performed conti nuously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written afte r referencing the txbfn bit to prevent writing to the txbn register by mistake. this register is read-only in 8-bit or 1-bit units. after reset, asifn is cleared to 00h. 7 0 asifn (n = 0, 1) 6 0 5 0 4 0 3 0 2 0 <1> txbfn <0> txsfn after reset: 00h r address: asif0 fffffa05h, asif1 fffffa15h txbfn transmission buffer data flag 0 data to be transferred next to txbn register does not exist (when the asimn.uarten or asimn.txen bit is cleared to 0, or when data has been transf erred to the transmis sion shift register) 1 data to be transferred next exists in txbn register (d ata exists in txbn register when the txbn register has been written to) ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 361 (4) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for stor ing parallel data that had been converted by the receive shift register. when reception is enabled (asimn.rxen bit = 1), receive da ta is transferred from the receive shift register to the rxbn register, synchronized with the completion of th e shift-in processing of one frame. also, a reception completion interrupt request signal (intsrn) is gener ated by the transfer to the rxbn register. for information about the timing for generat ing this interrupt request, refer to 14.5.4 receive operation . if reception is disabled (asimn.rxen bit = 0), the contents of the rxbn register are retained, and no processing is performed for transferring data to the r xbn register even when the shift-in processing of one frame is completed. also, the intsrn signal is not generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error (asisn.oven bit = 1) occurs, the receive data at that time is not trans ferred to the rxbn register. the rxbn register becomes ffh when a reset is input or asimn.uarten bit = 0. this register is read-only in 8-bit units. 7 rxbn7 rxbn (n = 0, 1) 6 rxbn6 5 rxbn5 4 rxbn4 3 rxbn3 2 rxbn2 1 rxbn1 0 rxbn0 after reset: ffh r address: rxb0 fffffa02h, rxb1 fffffa12h
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 362 (5) transmit buffer register n (txbn) the txbn register is an 8-bit buffe r register for setting transmit data. when transmission is enabled (asimn.txen bit = 1), the tr ansmit operation is started by writing data to txbn register. when transmission is disabled (txen bit = 0), even if data is written to the txbn regist er, the value is ignored. the txbn register data is transferr ed to the transmit shift register, and a transmission completion interrupt request signal (intstn) is generated, synchronized wit h the completion of the transmission of one frame from the transmit shift register. for information about t he timing for generating this interrupt request, refer to 14.5.2 transmit operation . when the asifn.txbfn bit = 1, writing must not be performed to the txbn register. this register can be read or written in 8-bit units. after reset, txbn is set to ffh. 7 txbn7 txbn (n = 0, 1) 6 txbn6 5 txbn5 4 txbn4 3 txbn3 2 txbn2 1 txbn1 0 txbn0 after reset: ffh r/w address: txb0 fffffa04h, txb1 fffffa14h
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 363 14.4 interrupt requests the following three types of interrupt re quest signals are generated from uartn. ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 364 14.5 operation 14.5.1 data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consists of one data fr ame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 14-2. the character bit length within one data frame, the type of parity, and the stop bit length are specified according to the asimn register. also, data is transferred lsb first. figure 14-2. format of uartn transmit/receive data 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 365 14.5.2 transmit operation when the asimn.uarten bit is set to 1, a hi gh level is output from the txdn pin. then, when the asimn.txen bit is set to 1, transmission is enabled, and the transmit operat ion is started by writing transmit data to the txbn register. (1) transmission enabled state this state is set by the txen bit. ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 366 figure 14-3. uartn transmission completion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn (output) (a) stop bit length: 1 (b) stop bit length: 2 stop
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 367 14.5.3 continuous transmission operation uartn can write the next transmit data to the txbn register at the timing t hat the transmit shift register starts the shift operation. this enables an efficient transmission rate to be realized by continuously transmitting data even during the transmission completion interrupt service after th e transmission of one data frame. in addition, reading the asifn.txsfn bit after the occurrence of a transmission co mpletion interrupt request si gnal (intstn) enables the txbn register to be efficiently written twice (2 byte s) without waiting for the tr ansmission of 1 data frame. when continuous transmission is perform ed, data should be written after referenc ing the asifn register to confirm the transmission status and whether or not da ta can be written to the txbn register. caution the values of the asif.txbfn and asif .txsfn bits change 10
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 368 figure 14-4. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write transmit data to txbn register write second byte transmit data to txbn register write transmit data to txbn register when reading asifn register, txbfn = 0? when reading asifn register, txsfn = 1? when reading asifn register, txsfn = 0? no no no no yes yes yes yes end of transmission processing
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 369 (1) starting procedure the procedure to start continuous transmission is shown below. figure 14-5. continuous tr ansmission starting procedure txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn, txsfn bits) 00 11 note 11 01 01 11 01 11 txsn register start bit stop bit stop bit start bit 10 note refer to 14.7 cautions (2) . asifn register transmission starting procedure internal operation txbfn txsfn ? <1> start transmission unit 0 0 ? 1 0 <2> generate start bit ? start data (1) transmission 1 0 0 0 1 note 1 1 1 ? <> 1 1 <3> intstn interrupt occurs ? 0 0 1 1 ? write data (3) <4> generate start bit start data (2) transmission <> 1 1 <5> intstn interrupt occurs ? 0 0 1 1 ? 1 1 note refer to 14.7 cautions (2) .
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 370 (2) ending procedure the procedure for ending continuous transmission is shown below. figure 14-6. continuous transmission end procedure txdn (output) data (m ? ? ? transmission end procedure internal operation txbfn txsfn <6> transmission of data (m ? ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? ? read asifn register (confirm that txsfn bit = 1) there is no write data <10> generate start bit start data (m) transmission <> 0 0 1 1 <11> generate intstn interrupt ? read asifn register (confirm that txsfn bit = 0) ? clear (0) the uarten bit or txen bit initialize internal circuits 0 0 0 0
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 371 14.5.4 receive operation the awaiting reception state is set by setting the asimn.uar ten bit to 1 and then setting the asimn.rxen bit to 1. to start the receive operatio n, start sampling at the fallin g edge when the falling of the rxdn pin is detected. if the rxdn pin is low level at a start bit sampling point, the st art bit is recognized. when the receive operation begins, serial data is stored sequentially in the receive shift regi ster according to the baud rate that was set. a reception completion interrupt request signal (intsrn) is generated each time the reception of one frame of data is completed. normally, the receive data is transferred from the rxbn register to memory by th is interrupt servicing. (1) reception enabled state the receive operation is set to the reception enabled state by setting the rxen bit to 1. ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 372 figure 14-7. uartn reception completion inte rrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read th e rxbn register even when a recept ion error occurs. if the rxbn register is not read, an overrun error wil l occur at the next data reception and the reception error status will continue infinitely. 2. reception is always performed assuming a stop bit length of 1. a second stop bit is ignored. 14.5.5 reception error the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. as a result of data reception, the various flags of the asisn register ar e set (1), and a reception error interrupt request signal (intsren) or a reception completion interrupt request signal (intsrn) is generated at the same time. the asimn.isrmn bit specifies whether the intsren signal or the intsrn signal is generated. the type of error that occurred during reception can be de tected by reading the conten ts of the asisn register during the intsren or intsrn interrupt servicing. the contents of the asisn r egister are cleared (0) by reading the asisn register. table 14-3. reception error causes error flag reception error cause pen parity error the parity specificat ion during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from the rxbn register
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 373 (1) separation of reception e rror interrupt request signal a reception error interrupt request signal can be separ ated from the intsrn signal and generated as the intsren signal by clearing the isrmn bit to 0. figure 14-8. when reception error inte rrupt request signal is separated from intsrn signal (isrmn bit = 0) (a) no error occurs during reception (b) an e rror occurs during reception intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn does not occur figure 14-9. when reception error in terrupt request signal is included in intsrn signal (isrmn bit = 1) (a) no error occurs during reception (b) an erro r occurs during reception intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsren does not occur
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 374 14.5.6 parity types and corresponding operation a parity bit is used to detect a bit error in communication da ta. normally, the same type of parity bit is used on the transmission and reception sides. (1) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the valu e ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 375 14.5.7 receive data noise filter the rxdn signal is sampled at the risi ng edge of the prescaler output base clock (f uclk ). if the same sampling value is obtained twice, the ma tch detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to figure 14-11 ). refer to 14.6.1 (1) base clock regarding the base clock. also, since the circuit is configured as shown in figure 14-10, internal processing during a receive operation is delayed by up to 2 clocks accordin g to the external signal status. figure 14-10. noise filter circuit rxdn q base clock in ld_en q in internal signal a internal signal b match detector f uclk figure 14-11. timing of rx dn signal judg ed as noise internal signal a base clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 376 14.6 dedicated baud rate generator n (brgn) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by uartn. the dedicated baud ra te generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. 14.6.1 baud rate generator n (brgn) configuration figure 14-12. configuration of baud rate generator n (brgn) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 asck0 note 2 f uclk note 1 selector uarten 8-bit counter match detector baud rate brgcn: mdln7 to mdln0 1/2 uarten and txen bits (or rxen bit) cksrn: tpsn3 to tpsn0 f xx notes 1. set f uclk so as to satisfy the following conditions. ? v dd = 4.0 to 5.5 v: f uclk 12 mhz ? v dd = 2.7 to 4.0 v: f uclk 6 mhz 2. asck0 pin input can be used only by uart0. remark f xx : main clock frequency (1) base clock when the asimn.uarten bit = 1, the clock selected a ccording to the cksrn.tpsn3 to cksrn.tpsn0 bits is supplied to the transmission/reception uni t. this clock is called the base clock (f uclk ). when the uarten bit = 0, f uclk is fixed to low level.
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 377 14.6.2 serial clock generation a serial clock can be generated according to the settings of the cksrn and brgcn registers. the base clock to the 8-bit counter is select ed by the cksrn.tpsn3 to cksrn.tpsn0 bits. the 8-bit counter divisor value can be set by the brgcn.mdln7 to brgcn.mdln0 bits. (1) clock select register n (cksrn) the cksrn register is an 8-bit register for selecting the base clock using the tpsn3 to tpsn0 bits. the clock selected by the tpsn3 to t psn0 bits becomes the base clock (f uclk ) of the transmission/reception module. this register can be read or written in 8-bit units. after reset, cksrn is cleared to 00h. caution clear the asimn.uarten bit to 0 before rewriti ng the tpsn3 to tpsn0 bits. 7 0 cksrn (n = 0, 1) 6 0 5 0 4 0 3 tpsn3 2 tpsn2 1 tpsn1 0 tpsn0 after reset: 00h r/w address: cksr0 fffffa06h, cksr1 fffffa16h tpsn3 tpsn2 tpsn1 tpsn0 base clock (f uclk ) note 1 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1,024 1 0 1 1 external clock note 2 (asck0 pin) other than above setting prohibited notes 1. set f uclk so as to satisfy the following conditions. ? v dd = 4.0 to 5.5 v: f uclk 12 mhz ? v dd = 2.7 to 4.0 v: f uclk 6 mhz 2. asck0 pin input clock can be used only by uart0. setting of uart1 is prohibited. remark f xx : main clock frequency
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 378 (2) baud rate generator c ontrol register n (brgcn) the brgcn register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uartn. this register can be read or written in 8-bit units. after reset, brgcn is set to ffh. caution if the mdln7 to mdln0 bits are to be o verwritten, the asimn.txen and asimn.rxen bits should be cleared to 0 first. 7 mdln7 brgcn (n = 0, 1) 6 mdln6 5 mdln5 4 mdln4 3 mdln3 2 mdln2 1 mdln1 0 mdln0 after reset: ffh r/w address: brgc0 fffffa07h, brgc1 fffffa17h mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 set value (k) serial clock 0 0 0 0 0
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 379 (3) baud rate the baud rate is the value obtained by the following formula. baud rate [bps] = f uclk = frequency [hz] of base clock selected by cksrn.tpsn3 to cksrn.tpsn0 bits. k = value set by brgcn.mdln7 to brgcn. mdln0 bits (k = 8, 9, 10, ..., 255) (4) baud rate error the baud rate error is obtained by the following formula. error (%) = ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 380 14.6.3 baud rate setting example table 14-4. baud rate generator setting data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) f uclk k err f uclk k err f uclk k err 300 f xx /512 41h (65) 0.16 f xx /1024 1ah (26) 0.16 f xx /256 41h (65) 0.16 600 f xx /256 41h (65) 0.16 f xx /1024 0dh (13) 0.16 f xx /128 41h (65) 0.16 1200 f xx /128 41h (65) 0.16 f xx /512 0dh (13) 0.16 f xx /64 41h (65) 0.16 2400 f xx /64 41h (65) 0.16 f xx /256 0dh (13) 0.16 f xx /32 41h (65) 0.16 4800 f xx /32 41h (65) 0.16 f xx /128 0dh (13) 0.16 f xx /16 41h (65) 0.16 9600 f xx /16 41h (65) 0.16 f xx /64 0dh (13) 0.16 f xx /8 41h (65) 0.16 10400 f xx /64 0fh (15) 0.16 f xx /64 0ch (12) 0.16 f xx /32 0fh (15) 0.16 19200 f xx /8 41h (65) 0.16 f xx /32 0dh (13) 0.16 f xx /4 41h (65) 0.16 24000 f xx /32 0dh (13) 0.16 f xx /2 a7h (167) ? 0dh (13) 0.16 31250 f xx /32 0ah (10) 0.00 f xx /32 08h (8) 0.00 f xx /16 0ah (10) 0 33600 f xx /2 95h (149) ? 77h (119) 0.04 f xx 95h (149) ? 41h (65) 0.16 f xx /16 0dh (13) 0.16 f xx /2 41h (65) 0.16 48000 f xx /16 0dh (13) 0.16 f xx /2 53h (83) 0.40 f xx /8 0dh (13) 0.16 56000 f xx /2 59h (89) 0.32 f xx /2 47h (71) 0.60 f xx 59h (89) 0.32 62500 f xx /16 0ah (10) 0.00 f xx /16 08h (8) 0.00 f xx /8 0ah (10) 0.00 76800 f xx /2 41h (65) 0.16 f xx /8 0dh (13) 0.16 f xx 41h (65) 0.16 115200 f xx /2 2bh (43) 0.94 f xx /2 23h (35) ? 2bh (43) 0.94 153600 f xx /2 21h (33) ? 0dh (13) 0.16 f xx 21h (33) ? 08h (8) 0 f xx /2 0dh (13) ? 08h (8) 0.00 caution the allowable fre quency of the base clock (f uclk ) is as follows. ? ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 381 14.6.4 allowable baud ra te range during reception the degree to which a discrepancy from the transmission des tination?s baud rate is allowed during reception is shown below. caution the equations described belo w should be used to set the ba ud rate error during reception so that it always is within the allowable error range. figure 14-13. allowable baud rate range during reception fl 1 data frame (11 + = ? ? =
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 382 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brmax = (flmin/11) ? ? = + ? = ? = ? ?
chapter 14 asynchronous serial interface (uart) preliminary user?s manual u16892ej1v0ud 383 14.6.5 transfer rate duri ng continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. however, on the reception si de, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 14-14. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f uclk yields the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows (when the stop bit length = 1). transfer rate = 11
preliminary user?s manual u16892ej1v0ud 384 chapter 15 clocked serial interface 0 (csi0) in the v850es/ke1, two channels of clocked serial interface 0 (csi0) are provided. 15.1 features ? ? ? ? ? ? ? ? ? ? ?
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 385 15.2 configuration csi0n is controlled via the csim0n register. (1) clocked serial interface mode register 0n (csim0n) the csim0n register is an 8-bit register t hat specifies the operation of csi0n. (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register that co ntrols the csi0n serial transfer operation. (3) serial i/o shift register 0n (sio0n) the sio0n register is a 16-bit shift register th at converts parallel data into serial data. the sio0n register is used for bot h transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by accessing the buffer register. (4) serial i/o shift register 0nl (sio0nl) the sio0nl register is an 8-bit shift register that converts parallel data into serial data. the sio0nl register is used for both transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations are started up by accessing the buffer register. (5) clocked serial interface recei ve buffer register n (sirbn) the sirbn register is a 16-bit buffer r egister that stores receive data. (6) clocked serial interface recei ve buffer register nl (sirbnl) the sirbnl register is an 8-bit buffer r egister that stores receive data. (7) clocked serial interface read-only r eceive buffer register n (sirben) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. (8) clocked serial interface read-only r eceive buffer register nl (sirbenl) the sirbenl register is an 8-bit buffer register that stores receive data. the sirbenl register is the same as the sirbnl register. it is used to read the contents of the sirbnl register. (9) clocked serial interface transm it buffer register n (sotbn) the sotbn register is a 16-bit buffer r egister that stores transmit data. (10) clocked serial interface transm it buffer register nl (sotbnl) the sotbnl register is an 8-bit buffer register that stores transmit data. (11) clocked serial interface initial tr ansmit buffer register n (sotbfn) the sotbfn register is a 16-bit buffer register that st ores the initial transmit data in the continuous transfer mode.
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 386 (12) clocked serial interface initial tran smit buffer register nl (sotbfnl) the sotbfnl register is an 8-bit buffe r register that stores initial tran smit data in the continuous transfer mode. (13) selector the selector selects the serial clock to be used. (14) serial clock controller controls the serial clock supply to the shift register. also controls the clock out put to the sck0n pin when the internal clock is used. (15) serial clock counter counts the serial clock output or i nput during transmission/reception, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) interrupt controller controls the interrupt request timing. remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 387 figure 15-1. block diagram of clocked serial interface selector transmission control so selection so latch transmit buffer register (sotbn/sotbnl) receive buffer register (sirbn/sirbnl) shift register (sio0n/sio0nl) initial transmit buffer register (sotbfn/sotbfnl) interrupt controller clock start/stop control & clock phase control serial clock controller sck0n intcsi0n so0n si0n control signal transmission data control f xx /2 6 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 f xx /2 to5n sck0n remarks 1. n = 0, 1 2. f xx : main clock frequency
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 388 15.3 registers (1) clocked serial interface mode register 0n (csim0n) the csim0n register controls the csi0n operation. this register can be read or written in 8-bit or 1-bit units (however, csotn bit is read-only). after reset, csim0n is cleared to 00h. caution overwriting the trmdn, ccln, dirn, csi tn, and auton bits can be done only when the csotn bit = 0. if these bits are overwritten when the csotn bit = 1, the operation cannot be guaranteed.
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 389 <7> csi0en csim0n (n = 0, 1) <6> trmdn 5 ccln <4> dirn 3 csitn 2 auton 1 0 <0> csotn after reset: 00h r/w address: csim00 fffffd00h, csim01 fffffd10h csi0en csi0n operation enable/disable 0 disable csi0n operation. 1 enable csi0n operation. the internal csi0n circuit can be reset note asynchronously by clearing the csi0en bit to 0. for the sck0n and so0n pin output status when the csi0en bit = 0, refer to 15.5 output pins . trmdn specification of transmission/reception mode 0 receive-only mode 1 transmission/reception mode when the trmdn bit = 0, reception is performed and the so0n pi n outputs a low level. data reception is started by reading the sirbn register. when the trmdn bit = 1, transmissi on/reception is started by writing data to the sotbn register. ccln specification of data length 0 8 bits 1 16 bits dirn specification of transfer direction mode (msb/lsb) 0 first bit of transfer data is msb 1 first bit of transfer data is lsb csitn control of delay of interrupt request signal 0 no delay 1 delay mode (interrupt request signal is delay ed 1/2 cycle compared to the serial clock) the delay mode (csitn bit = 1) is valid only in the master mode (csicn.cks0n2 to csicn.cks0n0 bits are not 111b). in the slave mode (cks0n2 to cks0n0 bits are 111b), do not set the delay mode. auton specification of single trans fer mode or continuous transfer mode 0 single transfer mode 1 continuous transfer mode csotn communication status flag 0 communication stopped 1 communication in progress the csotn bit is cleared (0) by writing 0 to the csi0en bit. note the csotn bit and the sirbn, sirbnl, sirbe, sirbenl, sion , and sionl registers are reset.
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 390 (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register t hat controls the csi0n transfer operation. this register can be read or written in 8-bit or 1-bit units. after reset, csicn is cleared to 00h. caution the csicn register can be overwri tten only when the csim0n.csi0en bit = 0. 7 0 csicn (n = 0, 1) 6 0 5 0 4 ckpn 3 dapn 2 cks0n2 1 cks0n1 0 cks0n0 after reset: 00h r/w address: csic0 fffffd01h, csic1 fffffd11h ckpn dapn specification of timing of transmitting/receiving data to/from sck0n 0 0 (type 1) do7 do6 do5 do4 do3 do2 do1 do0 di7 so0n (output) sck0n (i/o) si0n (input) di6 di5 di4 di3 di2 di1 di0 0 1 (type 2) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 1 0 (type 3) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 1 1 (type 4) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) cks0n2 cks0n1 cks0n0 serial clock note mode 0 0 0 f xx /2 master mode 0 0 1 f xx /2 2 master mode 0 1 0 f xx /2 3 master mode 0 1 1 f xx /2 4 master mode 1 0 0 f xx /2 5 master mode 1 0 1 f xx /2 6 master mode 1 1 0 clock generated by to5n master mode 1 1 1 external clock (sck0n pin) slave mode note set the serial clock so as to satisfy the following conditions. ? ?
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 391 (3) clocked serial interface receive buffe r registers n, nl (sirbn, sirbnl) the sirbn register is a 16-bit buffer r egister that stores receive data. when the receive-only mode is set (csim0n.trmdn bit = 0), the reception operati on is started by reading data from the sirbn register. this register is read-only in 16-bit units. when the lowe r 8 bits are used as the sirbnl register, this register is read-only in 8-bit units. in addition to reset input, this register is also clear ed to 0000h by clearing (0) the csim0n.csi0en bit. cautions 1. read the sirbn regist er only when a 16-bit data length has been set (csim0n.ccln bit = 1). read the sirbnl register only when an 8-bi t data length has been set (ccln bit = 0). 2. when the single transfer mode has been set (csim0n.aut on bit = 0), perform a read operation only in the idle state (csim0n.csotn bit = 0). if the sirbn or sirbnl register is read during data transfer, th e data cannot be guaranteed. (a) sirbn register 14 sirbn 14 13 sirbn 13 12 sirbn 12 2 sirbn 2 3 sirbn 3 4 sirbn 4 5 sirbn 5 6 sirbn 6 7 sirbn 7 8 sirbn 8 9 sirbn 9 10 sirbn 10 11 sirbn 11 15 sirbn 15 1 sirbn 1 0 sirbn 0 sirbn (n = 0, 1) after reset: 0000h r address: sirb0 fffffd02h, sirb1 fffffd12h (b) sirbnl register 7 sirbn7 sirbnl (n = 0, 1) 6 sirbn6 5 sirbn5 4 sirbn4 3 sirbn3 2 sirbn2 1 sirbn1 0 sirbn0 after reset: 00h r address: sirb0l fffffd02h, sirb1l fffffd12h
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 392 (4) clocked serial interface read-only receive buffer registers n, nl (sirben, sirbenl) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. even if the sirben register is read, the next operation will not start. the sirben register is used to read the conten ts of the sirbn register when the serial reception is not continued. this register is read-only in 16-bit units. however, when the lower 8 bits are used as the sirbenl register, the register is read-only in 8-bit units. in addition to reset input, this register is also clear ed to 0000h by clearing (0) the csim0n.csi0en bit. cautions 1. the receive operation is not started even if data is read from the sirben and sirbenl registers. 2. the sirben register can be read only if a 16-bit data length has been set (csim0n.ccln bit = 1). the sirbenl register can be read only if an 8-bit data length has been set (ccln bit = 0). (a) sirben register 14 sirben 14 13 sirben 13 12 sirben 12 2 sirben 2 3 sirben 3 4 sirben 4 5 sirben 5 6 sirben 6 7 sirben 7 8 sirben 8 9 sirben 9 10 sirben 10 11 sirben 11 15 sirben 15 1 sirben 1 0 sirben 0 sirben (n = 0, 1) after reset: 0000h r address: sirbe0 fffffd06h, sirbe1 fffffd16h (b) sirbenl register 7 sirben7 sirbenl (n = 0, 1) 6 sirben6 5 sirben5 4 sirben4 3 sirben3 2 sirben2 1 sirben1 0 sirben0 after reset: 00h r address: sirbe0l fffffd06h, sirbe1l fffffd16h
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 393 (5) clocked serial interface transmit bu ffer registers n, nl (sotbn, sotbnl) the sotbn register is a 16-bit buffer r egister that stores transmit data. when the transmission/reception mode is set (csim0n.trmd n bit = 1), the transmission operation is started by writing data to the sotbn register. this register can be read or written in 16-bit units. however, when the lower 8 bi ts are used as the sotbnl register, the register can be read or written in 8-bit units. after reset, this register is cleared to 0000h. cautions 1. access the sotbn register only when a 16-bit data length has been set (csim0n.ccln bit = 1). access the sotbnl register only when an 8-bi t data length has been set (ccln bit = 0). 2. when the single transfer mode is set (csim0n.auton bit = 0) , perform access only in the idle state (csim0n.csotn bit = 0). if the sotbn and sotbnl registers are accessed during data transfer, the da ta cannot be guaranteed. (a) sotbn register 14 sotbn 14 13 sotbn 13 12 sotbn 12 2 sotbn 2 3 sotbn 3 4 sotbn 4 5 sotbn 5 6 sotbn 6 7 sotbn 7 8 sotbn 8 9 sotbn 9 10 sotbn 10 11 sotbn 11 15 sotbn 15 1 sotbn 1 0 sotbn 0 sotbn (n = 0, 1) after reset: 0000h r/w address: sotb0 fffffd04h, sotb1 fffffd14h (b) sotbnl register 7 sotbn7 sotbnl (n = 0, 1) 6 sotbn6 5 sotbn5 4 sotbn4 3 sotbn3 2 sotbn2 1 sotbn1 0 sotbn0 after reset: 00h r/w address: sotb0l fffffd04h, sotb1l fffffd14h
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 394 (6) clocked serial interface initial transmit buffer registers n, nl (sotbfn, sotbfnl) the sotbfn register is a 16-bit buffer register that st ores initial transmission data in the continuous transfer mode. the transmission operation is not started even if data is writt en to the sotbfn register. this register can be read or written in 16-bit units. however, when the lower 8 bits are used as the sotbfnl register, the register can be read or written in 8-bit units. after reset, this register is cleared to 0000h. caution access the sotbfn register and sotbfnl regi ster only when a 16-bit data length has been set (csim0n.ccln bit = 1), and only when an 8- bit data length has been set (ccln bit = 0), respectively, and only in the idle state (csim0n.csotn bit = 0). if the sotbfn and sotbfnl registers are accessed during data transfer, the data cannot be guaranteed. (a) sotbfn register 14 sotbfn 14 13 sotbfn 13 12 sotbfn 12 2 sotbfn 2 3 sotbfn 3 4 sotbfn 4 5 sotbfn 5 6 sotbfn 6 7 sotbfn 7 8 sotbfn 8 9 sotbfn 9 10 sotbfn 10 11 sotbfn 11 15 sotbfn 15 1 sotbfn 1 0 sotbfn 0 sotbfn (n = 0, 1) after reset: 0000h r/w address: sotbf0 fffffd08h, sotbf1 fffffd18h (b) sotbfnl register 7 sotbfn7 sotbfnl (n = 0, 1) 6 sotbfn6 5 sotbfn5 4 sotbfn4 3 sotbfn3 2 sotbfn2 1 sotbfn1 0 sotbfn0 after reset: 00h r/w address: sotbf0l fffffd08h, sotbf1l fffffd18h
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 395 (7) serial i/o shift registers n, nl (sio0n, sio0nl) the sio0n register is a 16-bit shift register th at converts parallel data into serial data. the transfer operation is not started even if the s io0n register is read. this register is read-only in 16-bit units. however, when the lower 8 bi ts are used as the sio0nl register, the register is read-only in 8-bit units. in addition to reset input, this register is also clear ed to 0000h by clearing (0) the csim0n.csi0en bit. caution read the sio0n register and sio0nl re gister only when a 16-bi t data length has been set (csim0n.ccln bit = 1), and only when an 8-bit data length has been set (ccln bit = 0), respectively, and only in the idle state (csim0n.csotn bit = 0). if the sio0n and sio0nl registers are read during data tran sfer, the data cannot be guaranteed. (a) sio0n register 14 sion14 13 sion13 12 sion12 2 sion2 3 sion3 4 sion4 5 sion5 6 sion6 7 sion7 8 sion8 9 sion9 10 sion10 11 sion11 15 sion15 1 sion1 0 sion0 sio0n (n = 0, 1) after reset: 0000h r address: sio00 fffffd0ah, sio01 fffffd1ah (b) sio0nl register 7 sion7 sio0nl (n = 0, 1) 6 sion6 5 sion5 4 sion4 3 sion3 2 sion2 1 sion1 0 sion0 after reset: 00h r address: sio00l fffffd0ah, sio01l fffffd1ah
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 396 receive-only mode ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 397 15.4 operation 15.4.1 transmission/reception completion interrupt request signal (intcsi0n) the intcsi0n signal is set (1) upon comple tion of data transmission/reception. writing to the csim0n register clears (0) the intcsi0n signal. caution the delay mode (csim0n.csi tn bit = 1) is valid only in th e master mode (csicn.cks0n2 to csicn.cks0n0 bits are not 111b). the delay m ode cannot be set when the slave mode is set (cks0n2 to cks0n0 bits = 111b).
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 398 figure 15-2. timing chart of intcsi0n signal output in delay mode (a) transmit/receive type 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n signal csotn bit delay (b) transmit/receive type 4 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n signal csotn bit delay remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 399 15.4.2 single transfer mode (1) usage in the receive-only mode (csim0n.trmdn bit = 0), co mmunication is started by reading the sirbn/sirbnl register. in the transmission/reception mode (trmdn bit = 1) , communication is started by writing to the sotbn/sotbnl register. in the slave mode, the operation must be en abled beforehand (csim0n.csi0en bit = 1). when communication is started, t he value of the csim0n.csotn bit becomes 1 (transmission execution status). upon communication completion, the transmission/recepti on completion interrupt request signal (intcsi0n) is generated, and the csotn bit is cleared (0). t he next data communication request is then waited for. caution when the csotn bit = 1, do not manipulate the csi0n register. remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 400 figure 15-3. timing chart in single transfer mode (1/2) (a) in transmission/recepti on mode, data length: 8 bits , transfer direction: msb first, no interrupt delay, single transfer mode, when aah is received and 55h is transmitted, transmit/receive type 1 01010101 10101010 (55h) (aah) aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n signal 55h (transmit data) write 55h to sotbnl register remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. for the transmit/receive types, refer to 15.3 (2) clocked serial interface clock selection register n (csicn) . 3. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 401 figure 15-3. timing chart in single transfer mode (2/2) (b) in transmission/reception mode, da ta length: 8 bits, transfer directi on: msb first, no interrupt delay, single transfer mode, when aah is received and 55h is transmitted, transmit/receive type 2 01010101 10101010 aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n signal (55h) (aah) 55h (transmit data) write 55h to sotbnl register remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. for the transmit/receive types, refer to 15.3 (2) clocked serial interface clock selection register n (csicn) . 3. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 402 15.4.3 continuous transfer mode (1) usage (receive-only: 8-bit data length) <1> set the continuous transfer mode (csim0n. auton bit = 1) and the receive-only mode (csim0n.trmdn bit = 0). <2> read the sirbnl register (start transfer with dummy read). <3> when the transmission/reception completion interr upt request signal (intcs i0n) has been generated, read the sirbnl register note (reserve next transfer). <4> repeat step <3> (n ? ? ? ?
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 403 figure 15-4. continuous transf er (receive-only) timing chart ?
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 404 (2) usage (transmission/reception: 8-bit data length) <1> set the continuous transfer mode (csim0n.au ton bit = 1) and the transmission/reception mode (csim0n.trmdn bit = 1). <2> write the first data to the sotbfnl register. <3> write the 2nd data to the sotb nl register (start transfer). <4> when the transmission/reception completion interr upt request signal (intcs i0n) has been generated, write the next data to the sotbnl regi ster (reserve next transfer). re ad the sirbnl register to load the receive data. <5> repeat step <4> as long as data to be sent remains. <6> when the intcsi0n signal is generated, r ead the sirbnl register to load the (n ?
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 405 figure 15-5. continuous transfer (transmission/reception) timing chart ? < >< >< > < > < > < > < > < > < > < > < > < >
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 406 (3) next transfer reservation period in the continuous transfer mode, the next transfer mu st be prepared with the period shown in figure 15-6. figure 15-6. timing chart of next transfer reservation period (1/2) (a) when data length: 8 bits, transmit/receive type 1 sck0n (i/o) intcsi0n signal reservation period: 7 sck0n cycles (b) when data length: 16 bi ts, transmit/receive type 1 sck0n (i/o) intcsi0n signal reservation period: 15 sck0n cycles remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 407 figure 15-6. timing chart of next transfer reservation period (2/2) (c) when data length: 8 bi ts, transmit/receive type 2 sck0n (i/o) intcsi0n signal reservation period: 6.5 sck0n cycles (d) when data length: 16 bi ts, transmit/receive type 2 sck0n (i/o) intcsi0n signal reservation period: 14.5 sck0n cycles remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 408 (4) cautions to continue continuous transfers, it is necessary to either read the sirb n register or write to the sotbn register during the transfer reservation period. if access is performed to the sirbn register or the so tbn register when the transfer reservation period is over, the following occurs. (i) in case of conflict between transfer request clear and register access since transfer request clear has higher priority, the nex t transfer request is ignored. therefore, transfer is interrupted, and normal data transfer cannot be performed. figure 15-7. transfer request clear and register access conflict sck0n (i/o) intcsi0n signal rq_clr reg_r/w transfer reservation period remarks 1. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 409 (ii) in case of conflict between tr ansmission/reception completion inte rrupt request sign al (intcsi0n) generation and register access since continuous transfer has stopped once, ex ecuted as a new continuous transfer. in the slave mode, a bit phase erro r transfer error results (refer to figure 15-8 ). in the transmission/reception mode, the value of the so tbfn register is retransmitted, and illegal data is sent. figure 15-8. interrupt request and register ac cess conflict sck0n (i/o) intcsi0n signal rq_clr reg_r/w transfer reservation period 01 234 remarks 1. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) preliminary user?s manual u16892ej1v0ud 410 15.5 output pins the following describes the output pins. for the setting of each pin, refer to table 4-12 settings when port pins are used for alternate functions . (1) sck0n pin when the csi0n operation is disabled (csim0n.csi0en bi t = 0), the sck0n pin output status is as follows. table 15-2. sck0n pin output status ckpn cks0n2 cks0n1 cks0n0 sck0n pin output 0 don?t care don?t care don?t care fixed to high level 1 1 1 high impedance 1 other than above fixed to low level remark n = 0, 1 (2) so0n pin when the csi0n operation is disabled (csi0en bit = 0), the so0n pin output status is as follows. table 15-3. so0n pin output status trmdn dapn auton ccln dirn so0n pin output 0 don?t care don?t care don?t care don?t care fixed to low level 0 don?t care don?t care don?t care so latch value (low level) 0 sotbn7 bit value 0 1 sotbn0 bit value 0 sotbn15 bit value 0 1 1 sotbn0 bit value 0 sotbfn7 bit value 0 1 sotbfn0 bit value 0 sotbfn15 bit value 1 1 1 1 1 sotbfn0 bit value remark n = 0, 1
preliminary user?s manual u16892ej1v0ud 411 chapter 16 i 2 c bus to use the i 2 c bus function, set the p38/sda0 and p39/scl0 pins to n-ch open drain output as the alternate function. in the v850es/ke1, one channel of i 2 c bus is provided. the products with an on-chip i 2 c bus are shown below.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 412 figure 16-1. block diagram of i 2 c0 iice0 dq cl01, cl00 sda0 scl0 intiic0 f xx lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 cld0 dad0 smc0 dfc0 cl01 cl00 clx0 stcf0 iicbsy0 stcen0 iicrsv0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator match signal iic shift register 0 (iic0) so latch set clear n-ch open- drain output n-ch open- drain output data hold time correction circuit ack output circuit wakeup controller ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler start condition detector internal bus iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) iic flag register 0 (iicf0) start condition generator bus status detector
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 413 a serial bus configuration example is shown below. figure 16-2. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 414 16.2 configuration i 2 c0 includes the following hardware. table 16-1. configuration of i 2 c0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iiccf0) iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) (1) iic shift register 0 (iic0) the iic0 register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8- bit serial data. the iic0 register can be used for both transmission and reception. write and read operations to the iic0 r egister are used to control the act ual transmit and receive operations. the iic0 register can be read or written in 8-bit units. after reset, iic0 is cleared to 00h. (2) slave address register 0 (sva0) the sva0 register sets local addresses when in slave mode. the sva0 register can be read or written in 8-bit units. after reset, sva0 is cleared to 00h. (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wakeup controller this circuit generates an interrupt r equest signal (intiic0) when the address re ceived by this register matches the address value set to the sva0 register or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt is generated by the following two triggers. ? falling edge of the eighth or ninth clock of t he serial clock (set by iicc0.wtim0 bit) ? interrupt request generated when a stop condition is detected (set by iicc0.spie0 bit)
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 415 (8) serial clock controller in master mode, this circuit generates the clo ck output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector , start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start condition when the iicc0.stt0 bit is set. however, in the communication reservation disabled st atus (iicf0.iicrsv0 bit = 1), when the bus is not released (iicf0.iicbsy0 bit = 1), start condition requests are ignored and the iicf0.stcf0 bit is set to 1. (13) bus status detector this circuit detects whether or not the bus is rel eased by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediatel y following operation, the init ial status is set by the iicf0.stcen0 bit.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 416 16.3 registers i 2 c0 is controlled by the following registers. iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iicf0) iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) the following registers are also used. iic shift register 0 (iic0) slave address register 0 (sva0) remark for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions . (1) iic control register 0 (iicc0) the iicc0 register is used to enable/stop i 2 c0 operations, set wait timing, and set other i 2 c operations. the iicc0 register can be read or written in 8-bit or 1-bit units. after reset, iicc0 is cleared to 00h.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 417 (1/4) after reset: 00h r/w address: fffffd82h <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c0 operation enable/dis able specification 0 stop operation. reset the iics0 register note 1 . stop internal operation. 1 enable operation. condition for clearing (iice0 bit = 0) condition for setting (iice0 bit = 1) ? ? ? ? ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 418 (2/4) spie0 enable/disable generation of interr upt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 bit = 0) note condition for setting (spie0 bit = 1) ? ? ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 419 (3/4) stt0 start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). the sda0 line is changed from high level to low level and then the start condition is generated. next, afte r the rated amount of time has elapsed, the scl0 line is changed to low level. when a third party is communicating: ? ? ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 420 (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until the scl0 pin goes to high level. next, after the rated amount of time has elapsed, the sda0 line is changed from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acke0 bit has been cleared to 0 and during the wait period after slave has been notified of final reception. for master transmission: a stop condition cannot be generat ed normally during the ack signal period. set to 1 during the wait period. ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 421 (2) iic status register 0 (iics0) the iics0 register indica tes the status of the i 2 c0 bus. the iics0 register is read-only, in 8-bit or 1-bit units. after reset, iics0 is cleared to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the iics0 register using an access method that causes a wait. for details, refer to 3.4.8 (2). (1/3) after reset: 00h r address: fffffd86h <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 bit = 0) condition for setting (msts0 bit = 1) ? ? ? ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 422 (2/3) exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 bit = 0) condition for setting (exc0 bit = 1) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 423 (3/3) ackd0 detection of acknowledge signal (ack) 0 ack signal was not detected. 1 ack signal was detected. condition for clearing (ackd0 bit = 0) condition for setting (ackd0 bit = 1) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 424 (3) iic flag register 0 (iicf0) iicf0 is a register that sets the operation mode of i 2 c0 and indicates the status of the i 2 c bus. this register can be read or written in 8-bit or 1-bit units. however, the stcf0 and iicbsy0 bits are read-only. the iicrsv0 bit can be used to enable/disable t he communication reservation function (refer to 16.13 communication reservation ). the stcen0 bit can be used to set the in itial value of the iicbsy0 bit (refer to 16.14 cautions ). the iicrsv0 and stcen0 bits can be written only when the operation of i 2 c0 is disabled (iicc0.iice0 bit = 0). when operation is enabled, the iic f0 register can be read. after reset, iicf0 is cleared to 00h.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 425 <7> stcf0 condition for clearing (stcf0 bit = 0) cleared by the stt0 bit = 1 reset condition for setting (stcf0 bit = 1) generating start condition unsuccessful and the stt0 bit cleared to 0 when communication reservation is disabled (iicrsv0 bit = 1). stcf0 0 1 generate start condition start condition generation unsuccessful: clear stt0 flag iicc0.stt0 clear flag iicf0 <6> iicbsy0 5 0 4 0 3 0 2 0 <1> stcen0 <0> iicrsv0 after reset: 00h r/w note address: fffffd8ah condition for clearing (iicbsy0 bit = 0) detection of stop condition reset condition for setting (iicbsy0 bit = 1) detection of start condition setting of the iice0 bit when the stcen0 bit = 0 iicbsy0 0 1 bus release status bus communication status i 2 c0 bus status flag condition for clearing (stce0 bit = 0) detection of start condition reset condition for setting (stce0 bit = 1) setting by instruction stcen0 0 1 after operation is enabled (iice0 bit = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice0 bit = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv0 bit = 0) cleared by instruction reset condition for setting (iicrsv0 bit = 1) setting by instruction iicrsv0 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only bits. cautions 1. write to the stcen0 bit only wh en the operation is stopped (iice0 bit = 0). 2. as the bus release status (iicbsy0 bit = 0) is recognized regardless of the actual bus status when the stcen0 bit = 1, when gene rating the first start condition (stt0 bit = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. write to the iicrsv0 bit only when the operation is stopped (iice0 bit = 0).
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 426 (4) iic clock selection register 0 (iiccl0) the iiccl0 register is used to set the transfer clock for i 2 c0. the iiccl0 register can be r ead or written in 8-bit or 1-bit units. however, the cld0 and dad0 bits are read- only. the smc0, cl01, and cl00 bits are set in combination with the iicx0.clx0 bit (refer to 16.3 (6) i 2 c0 transfer clock setting method ). after reset, iiccl0 is cleared to 00h. after reset: 00h r/w note address: fffffd84h 7 6 <5> <4> 3 2 1 0 iiccl0 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 cld0 detection of scl0 pin level (valid only when iicc0.iice0 bit = 1) 0 the scl0 pin was detected at low level. 1 the scl0 pin was detected at high level. condition for clearing (cld0 bit = 0) condition for setting (cld0 bit = 1) ? ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 427 (5) iic function expansion register 0 (iicx0) this register sets the function expansion of i 2 c0 (valid only in high-speed mode). this register can be read or written in 8-bit or 1-bit units. the clx0 bit is set in combination with the iiccl0.smc0, iiccl0.cl01, and iiccl0.cl00 bits (refer to 16.3 (6) i 2 c0 transfer clock setting method ). after reset, iicx0 is cleared to 00h. after reset: 00h r/w address: fffffd85h 7 6 5 4 3 2 1 <0> iicx0 0 0 0 0 0 0 0 clx0 (6) i 2 c0 transfer clock setting method the i 2 c0 transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 428 table 16-2. selection clock setting iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock transfer clock (f xx /m) settable internal system clock frequency (f xx ) range operation mode 0 0 0 0 f xx /2 f xx /88 4.0 mhz to 8.38 mhz 0 0 0 1 f xx /2 f xx /172 8.38 mhz to 16.76 mhz 0 0 1 0 f xx f xx /86 4.19 mhz to 8.38 mhz 0 0 1 1 f xx /3 f xx /198 16.0 mhz to 19.8 mhz normal mode (smc0 bit = 0) 0 1 0 x f xx /2 f xx /48 8 mhz to 16.76 mhz 0 1 1 0 f xx f xx /24 4 mhz to 8.38 mhz 0 1 1 1 f xx/ 3 f xx /54 16 mhz to 20 mhz high-speed mode (smc0 bit = 1) 1 0 x x setting prohibited 1 1 0 x f xx /2 f xx /24 8.00 mhz to 8.38 mhz 1 1 1 0 f xx f xx /12 4.00 mhz to 4.19 mhz high-speed mode (smc0 bit = 1) 1 1 1 1 setting prohibited remark x: don?t care (7) iic shift register 0 (iic0) the iic0 register is used for serial transmission/reception (shift operations) t hat is synchronized with the serial clock. the iic0 register can be read or writt en in 8-bit units, but data should not be written to the iic0 register during a data transfer. when the iic0 register is written during wait, the wait is cancelled and dat a transfer is started. after reset, iic0 is cleared to 00h. after reset: 00h r/w address: fffffd80h 7 6 5 4 3 2 1 0 iic0 (8) slave address register 0 (sva0) the sva0 register holds the i 2 c bus?s slave addresses. the sva0 register can be read or written in 8-bit units, but bit 0 should be fixed as 0. after reset, sva0 is cleared to 00h. after reset: 00h r/w address: fffffd83h 7 6 5 4 3 2 1 0 sva0 0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 429 16.4 functions 16.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. scl0 .............. this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sda0 .............. this pi n is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial dat a bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 16-3. pin configuration diagram v dd scl0 sda0 scl0 sda0 v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 430 16.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition?, ?data?, and ?stop conditi on? output via the i 2 c bus?s serial data bus is shown below. figure 16-4. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scl0 sda0 start condition address r/w ack data data stop condition ack ack the master device outputs t he start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave dev ice (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master devic e. however, in the sl ave device, the scl0 pin?s low-level period can be extended and a wait can be inserted. 16.5.1 start condition a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are si gnals that the master device outputs to the slave device when starting a serial transfer. start conditions can be detected when the devic e is used as a slave. figure 16-5. start conditions h scl0 sda0 a start condition is output when the iicc0.stt0 bit is se t to 1 after a stop condition has been detected (iics0.spd0 bit = 1). when a start condition is detec ted, the iics0.std0 bit is set to 1.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 431 16.5.2 addresses the 7 bits of data that follow the st art condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via bus lines. t herefore, each slave devic e connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and che cks whether or not the 7-bit address data matches the data values stored in the sva0 register. if the address data matches the sva0 register values, the slave device is selected and communicate s with the master device until the mast er device transmits a start condition or stop condition. figure 16-6. address address scl0 1 sda0 intiic0 note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (int iic0) is generated if a local addre ss or extension code is received during slave device operation. the slave address and the eighth bit, which specif ies the transfer direction as described in 16.5.3 transfer direction specification below, are together written to the iic0 regi ster and are then output. received addresses are written to the iic0 register. the slave address is assigned to the hi gher 7 bits of the iic0 register. 16.5.3 transfer di rection specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfe r direction. when this transfer direction specification bit has a value of 0, it indicates that the mast er device is transmitting data to a slave device. when the transfer direction specif ication bit has a value of 1, it indica tes that the master device is receiving data from a slave device. figure 16-7. transfer direction specification scl0 1 sda0 intiic0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the interrupt request signal (int iic0) is generated if a local addre ss or extension code is received during slave device operation.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 432 16.5.4 acknowledge signal (ack) the acknowledge signal (ack) is used by the transmitting and re ceiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. t he transmitting device normally receives an ack signal after transmitting 8 bits of data. ho wever, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the trans mitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave dev ice does not return an ack signal, the master device outputs either a stop condition or a rest art condition and then stops the current tr ansmission. failure to return an ack signal may be caused by the following two factors. <1> reception was not performed normally. <2> the final data was received. when the receiving device sets the sda0 line to low leve l during the ninth clock, t he ack signal becomes active (normal receive response). when the iicc0.acke0 bit is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes the iics0.trc0 bit to be set. when this trc0 bit?s value is 0, it indicates receive mode. therefore, the acke0 bit should be set to 1. when the slave device is receiving (when trc0 bit = 0), if the slave device does not need to receive any more data after receiving several bytes, clearing the acke0 bit to 0 will prevent the mast er device from starting transmission of the subsequent data. similarly, when the master device is receiving (w hen trc0 bit = 0) and the subsequent data is not needed and when either a restart condition or a st op condition should therefore be output, cl earing the acke0 bit to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sda0 line (i.e., stops transmission) during transmissi on from the slave device. figure 16-8. acknowledge signal (ack) scl0 1 sda0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack when the local address is received, an ack signal is aut omatically output in synch ronization with the falling edge of the scl0 pin?s eighth clock regardless of the acke0 bit va lue. no ack signal is output if the received address is not a local address. the ack signal output method during dat a reception is based on the wait timing setting, as described below. ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 433 16.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that t he master device outputs to the slav e device when serial transfer has been completed. stop conditions can be detect ed when the device is used as a slave. figure 16-9. stop condition h scl0 sda0 a stop condition is generated when the ii cc0.spt0 bit is set to 1. when the stop condition is detected, the iics0.spd0 bit is set to 1 and the interrupt request signal (i ntiic0) is generated when the iicc0 .spie0 bit is set to 1.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 434 16.5.6 wait signal (wait) the wait signal (wait) is used to notif y the communication partner that a devic e (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave dev ices, the next data transfer can begin. figure 16-10. wait signal (1/2) (a) when master device has a nine-clock wa it and slave device has an eight-clock wait (master: transmission, slave: reception, and iicc0.acke0 bit = 1) scl0 6 sda0 78 9 123 scl0 iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iic0 data write (cancel wait) slave wait after output of eighth clock. ffh is written to iic0 register or iicc0.wrel0 bit is set to 1. transfer lines wait signal from slave wait signal from master
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 435 figure 16-10. wait signal (2/2) (b) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acke0 bit = 1) scl0 6 sda0 789 123 scl0 iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master and slave both wait after output of ninth clock. iic0 data write (cancel wait) slave ffh is written to iic0 register or wrel0 bit is set to 1. output according to previously set acke0 bit value transfer lines wait signal from master and slave wait signal from slave a wait may be automatically generated depending on the setting for the iicc0.wtim0 bit. normally, when the wrel0 bit is set to 1 or when ffh is wr itten to the iic0 register, t he wait status is canceled and the transmitting side writes data to the iic 0 register to cancel the wait status. the master device can also c ancel the wait status via ei ther of the following methods. by setting the iicc0.stt0 bit to 1 by setting the iicc0.spt0 bit to 1
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 436 16.6 i 2 c interrupt request signals (intiic0) the following shows the value of the iic s0 register at the intiic0 interr upt request signal generation timing and at the intiic0 signal timing. 16.6.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iicc0.wtim0 bit = 0 iicc0.spt0 bit = 1 ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 437 (2) start ~ address ~ data ~ star t ~ address ~ data ~ stop (restart) <1> when wtim0 bit = 0 iicc0.stt0 bit = 1 spt0 bit = 1 ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 438 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtim0 bit = 0 spt0 bit = 1 ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 439 16.6.2 slave device operation (when receiving slave address da ta (match with address)) (1) start ~ address ~ data ~ data ~ stop <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 440 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 441 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtim0 bit = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 442 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 443 16.6.3 slave device operation (w hen receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 444 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 445 (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtim0 bit = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 446 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 447 16.6.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? ? ? ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 448 (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 449 16.6.6 operation when arbitr ation loss occurs (no communicat ion after arbitration loss) (1) when arbitration loss occurs dur ing transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 450 ( 3) when arbitration loss occurs during data transfer <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 451 (4) when loss occurs due to rest art condition during data transfer <1> not extension code (example: mismatches with address) st ad6 to ad0 rw ak d7 to dm st ad6 to ad0 rw ak d7 to d0 ak sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 452 (5) when loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dm sp ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 453 (7) when arbitration loss occurs due to a stop conditi on when attempting to gene rate a restart condition when wtim0 bit = 1 stt0 bit = 1 ? ? ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 454 16.7 interrupt request signal (intiic0) generation timing and wait control the setting of the iicc0.wtim0 bit determines the ti ming by which the intiic 0 signal is generated and the corresponding wait control, as shown below. table 16-3. intiic0 signal gene ration timing and wait control during slave device operation du ring master device operation wtim0 bit address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic0 signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the addre ss set to the sva0 register. at this point, an ack signal is output regardless of the value set to the iicc0.acke0 bit. for a slave device that has received an extensi on code, the intiic0 signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the intiic0 signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not ma tch the contents of the sva0 regi ster and extensi on codes have not been received, neither the intiic0 signal nor a wait occurs. remark the numbers in the table indicate the number of the serial clock?s cl ock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 455 (4) wait cancellation method the four wait cancellation methods are as follows. ? ? ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 456 16.10 extension code (1) when the higher 4 bits of the receive address are eit her 0000 or 1111, the extension code flag (exc0) is set for extension code reception and an interrupt request signal (intiic0) is issued at the falling edge of the eighth clock. the local address stored in the sva0 register is not affected. (2) if 11110xx0 is set to the sva0 register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the int iic0 signal occurs at the fa lling edge of the eighth clock. ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 457 16.11 arbitration when several master devices simultaneous ly output a start condition (when the iicc0.stt0 bit is set to 1 before the iics0.std0 bit is set to 1), communication among the ma ster devices is performed as the number of clocks is adjusted until the data differs. this ki nd of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (iic s0.ald0 bit) is set (1) via the timing by which the arbitration loss occurr ed, and the scl0 and sda0 lines are both set for high impedance, which releases the bus. the arbitration loss is detec ted based on the timing of the next interrupt request signal (i ntiic0) (the eighth or ninth clock, when a stop condition is detec ted, etc.) and the ald0 bit = 1 se tting that has been made by software. for details of interrupt request timing, refer to 16.6 i 2 c interrupt request signals (intiic0) . figure 16-11. arbitration timing example master 1 master 2 transfer lines scl0 sda0 scl0 sda0 scl0 sda0 master 1 loses arbitration hi-z hi-z
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 458 table 16-5. status during arbitration and interrupt request generation timing status during arbitration inte rrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data reception when restart condition is det ected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected duri ng data transfer when stop condition is output (when iicc0.spie0 bit = 1) note 2 when the sda0 pin is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when spie0 bit = 1) note 2 when the sda0 pin is at low level while attempting to output a stop condition when the scl0 pin is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iicc0.wtim0 bit = 1, an intiic0 signal o ccurs at the falling edge of the ninth clock. when the wtim0 bit = 0 and the extension code?s slave address is received, an intiic0 signal occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spie0 bit = 1 for master device operation. 16.12 wakeup function the i 2 c bus slave function is a function t hat generates an interrupt request signal (intiic0) when a local address or extension code has been received. this function makes processing more effi cient by preventing the unnecessary intiic0 signal from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wak eup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detect ed, the iicc0.spie0 bit is set regardl ess of the wakeup function, and this determines whether the intiic0 signal is enabled or disabled.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 459 16.13 communication reservation 16.13.1 when communication reservation func tion is enabled (iicf0.iicrsv0 bit = 0) to start master device communications when not current ly using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is re leased. there are two modes under which the bus is not used. ? ?
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 460 the communication reservation timing is shown below. figure 16-12. communication reservation timing 2 13456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iic0 set spd0 and intiic0 stt0 =1 communication reservation set std0 output by master with bus access iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after the iics0.std0 bit is set to 1, a communication reservation can be made by setting the iicc0 .stt0 bit to 1 before a stop condition is detected. figure 16-13. timing for accep ting communication reservations scl0 sda0 std0 spd0 standby mode
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 461 the communication reservation flowchart is illustrated below. figure 16-14. communication reservation flowchart di stt0 = 1 define communication reservation wait cancel communication reservation no yes iic0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 462 16.13.2 when communication reservation func tion is disabled (iicf0.iicrsv0 bit = 1) when the iicc0.stt0 bit is set when the bus is not us ed in a communication during bus communication, this request is rejected and a start condition is not generated. the followi ng two statuses are incl uded in the status where bus is not used. ? when arbitration results in nei ther master nor slave operation ? when an extension code is received and slave operation is disabled (ack signal is not returned and the bus was released when the iicc0.lrel0 bit was set to 1) to confirm whether the start conditi on was generated or request was rejected, check the iicf0.stcf0 flag. the time shown in table 16-7 is required until the stcf0 flag is set after setting the s tt0 bit = 1. therefore, secure the time by software. table 16-7. wait periods cl01 cl00 wait period 0 0 6 clocks 0 1 6 clocks 1 0 3 clocks 1 1 9 clocks
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 463 16.14 cautions (1) when iicf0.stcen0 bit = 0 immediately after i 2 c0 operation is enabled, the bus communica tion status (iicf0.iicbsy0 bit = 1) is recognized regardless of the actual bus status. to execute master comm unication in the status where a stop condition has not been detect ed, generate a stop condition and then releas e the bus before st arting the master communication. use the following sequence for generating a stop condition. <1> set the iiccl0 register. <2> set the iicc0.iice0 bit. <3> set the iicc0.spt0 bit. (2) when iicf0.stcen0 bit = 1 immediately after i 2 c0 operation is enabled, the bus released status (iicbsy0 bit = 0) is recognized regardless of the actual bus status. to issue t he first start condition (iicc0.stt0 bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. 16.15 communication operations 16.15.1 master operation 1 the following shows the flowchart for master communi cation when the communication reservation function is enabled (iicf0.iicrsv0 bit = 0) and the master operation is started after a stop condition is detected (iicf0.stcen0 bit = 0).
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 464 figure 16-15. master operation flowchart (1) iicc0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 465 16.15.2 master operation 2 the following shows the flowchart for master communi cation when the communication reservation function is disabled (iicrsv0 bit = 1) and the ma ster operation is start ed without detecting a stop condition (stcen0 bit = 1). figure 16-16. master operation flowchart (2) no iiccl0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 466 16.15.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiic0 interrupt (processing requiring a significant change of the operat ion status, such as st op condition detection during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiic0 interrupt servicing performs only status change processing and t hat the actual data communication is performed during the main processing. figure 16-17. software out line during slave operation i 2 c intiic0 setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main pr ocessing instead of the intiic0 signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progre ss (valid address detection stop condition detection, ack signal from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. th is is the same status as an intiic0 interrupt during normal data transfer. this flag is set in the interrupt servicing block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the interrupt servicing bl ock, so the first data is transmitted without clearance proce ssing (the address match is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of the iics0.trc0 bit. the following shows the operati on of the main processing bl ock during slave operation. start i 2 c0 and wait for the communication enabled status. when communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmissi on operation until the master device stops returning ack signal. when the master device stops returning ac k signal, transfer is complete.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 467 for reception, receive the required num ber of data and do not return ack signal for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart c ondition. this causes exit from communications. figure 16-18. slave operation flowchart (1) yes yes yes yes yes yes yes yes no no no no no no no no start communication mode? communication mode? communication mode? ready? ready? read data clear ready flag clear ready flag communication direction flag = 1? wtim0 = 1 wrel0 = 1 acke0 = 0 wrel0 = 1 acke0 = wtim0 = 1 ackd0 = 1? wrel0 = 1 clear communication mode flag data processing data processing transfer completed? iic0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 468 the following shows an example of the pr ocessing of the slave device by an int iic0 interrupt (it is assumed that no extension codes are used here). during an intiic0 interr upt, the status is confirm ed and the following steps are executed. <1> when a stop condition is detect ed, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, the communica tion mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, w hen the ready flag is set, operation retu rns from the interrupt while the i 2 c0 bus remains in the wait status. remark <1> to <3> in the above correspond to <1> to <3> in figure 16-19 slave operation flowchart (2) . figure 16-19. slave operation flowchart (2) yes yes yes no no no intiic0 generated set ready flag interrupt servicing completed interrupt servicing completed interrupt servicing completed termination processing spd0 = 1? std0 = 1? coi0 = 1? lrel0 = 1 clear communication mode communication direction flag
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 469 16.16 timing of data communication when using i 2 c bus mode, the master device out puts an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the ma ster device transmits the iics0.trc0 bit that specifies the data transfer direction and then starts serial co mmunication with the slave device. the iic0 register?s shift operation is synchronized with the falling edge of the se rial clock (scl0 pin). the transmit data is transferred to the so latch and is output (msb first) via the sda0 pin. data input via the sda0 pin is captured by the iic0 register at the ri sing edge of the scl0 pin. the data communication timing is shown below.
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 470 figure 16-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 471 figure 16-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 472 figure 16-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 473 figure 16-21. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l h h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iic0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 474 figure 16-21. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0
chapter 16 i 2 c bus preliminary user?s manual u16892ej1v0ud 475 figure 16-21. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l h acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0
preliminary user?s manual u16892ej1v0ud 476 chapter 17 interrupt/except ion processing function 17.1 overview the v850es/ke1 is provided with a dedica ted interrupt controller (intc) fo r interrupt servicing and realize an interrupt function that can service interrupt r equests from a total of 33 or 34 sources. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/ke1 can process interrupt requests from t he on-chip peripheral hardware and external sources. moreover, exception processing can be star ted by the trap instruction (software exception) or by generation of an exception event (fetching of an illegal opcode) (exception trap). 17.1.1 features interrupt source v850es/ke1 external 1 channel (nmi pin) non-maskable interrupt internal 2 channels (wdt1, wdt2) external 7 channels (all edge detection interrupts) wdt1 1 channel tmp 3 channels tm0 2 channels tmh 2 channels tm5 2 channels wt 2 channels brg 1 channel uart 6 channels csi0 2 channels iic note 1 channel kr 1 channel ad 1 channel interrupt function maskable interrupt internal total 24 channels 16 channels (trap00h to trap0fh) software exception 16 channels (trap10h to trap1fh) exception function exception trap 2 channels (ilgop/dbg0) note only in the pd703207y, 70f3207hy table 17-1 lists the interrupt/exception sources.
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 477 table 17-1. interrupt source list (1/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset internal reset input from wdt1, wdt2 wdt1 wdt2 0000h 00000000h u ndefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? ? intwdt1 wdt1 overflow (when non- maskable interrupt selected) wdt1 0020h 00000020h note 1 ? non- maskable interrupt ? intwdt2 wdt2 overflow (when non- maskable interrupt selected) wdt2 0030h 00000020h note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal opcode/dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm1 wdt1 overflow (when interval timer selected) wdt1 0080h 00000080h nextpc wdt1ic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin valid edge input pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge input pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge input pin 00f0h 000000f0h nextpc pic6 10 inttm010 tm01 and cr010 match tm01 0120h 00000120h nextpc tm0ic10 11 inttm011 tm01 and cr011 match tm01 0130h 00000130h nextpc tm0ic11 12 inttm50 tm50 and cr50 match tm50 0140h 00000140h nextpc tm5ic0 13 inttm51 tm51 and cr51 match tm51 0150h 00000150h nextpc tm5ic1 14 intcsi00 csi00 transfer completion csi00 0160h 00000160h nextpc csi0ic0 15 intcsi01 csi01 transfer completion csi01 0170h 00000170h nextpc csi0ic1 16 intsre0 uart0 reception error occurrence uart0 0180h 00000180h nextpc sreic0 17 intsr0 uart0 reception completion uart0 0190h 00000190h nextpc sric0 18 intst0 uart0 transmission completion uart0 01a0h 000001ah nextpc stic0 19 intsre1 uart1 reception error occurrence uart1 01b0h 000001b0h nextpc sreic1 20 intsr1 uart1 reception completion uart1 01c0h 000001c0h nextpc sric1 maskable interrupt 21 intst1 uart1 transmission completion uart1 01d0h 000001d0h nextpc stic1 notes 1. for restoration in the case of intwdt1 and intwdt2, refer to 17.10 cautions . 2. n = 0 to fh
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 478 table 17-1. interrupt source list (2/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register 22 inttmh0 tmh0 and cmp00/cmp01 match tmh0 01e0h 000001e0h nextpc tmhic0 23 inttmh1 tmh1 and cmp10/cmp11 match tmh1 01f0h 000001f0h nextpc tmhic1 25 intiic0 note i 2 c0 transfer completion i 2 c0 0210h 00000210h nextpc iicic0 26 intad a/d conversion completion a/d 0220h 00000220h nextpc adic 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intwti watch timer interval wt 0240h 00000240h nextpc wtiic 29 intwt watch timer reference time wt 0250h 00000250h nextpc wtic 30 intbrg 8-bit counter of prescaler 3 and prscm match prescaler 3 0260h 00000260h nextpc brgic 45 inttp0ov tmp0 overflow tmp0 03a0h 000003a0h nextpc tp0ovic 46 inttp0cc0 tp0ccr0 capture/ tmp0 and tp0ccr0 match tmp0 03b0h 000003b0h nextpc tp0ccic0 maskable interrupt 47 inttp0cc1 tp0ccr1 capture/ tmp0 and tp0ccr1 match tmp0 03c0h 000003c0h nextpc tp0ccic1 note only in the pd703207y, 70f3207hy remarks 1. default priority: the priority order when two or more maskable interrupt requests with the same priority level are generated at the sa me time. the highest priority is 0. the priority of non-maskable interrupt request is as follows. intwdt2 > intwdt1 > nmi restored pc: the value of the program counter (pc) saved to eipc, fepc, or dbpc when interrupt/exception processing is started. the restored pc when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextpc (when an interrupt is acknowledged during the execution of an instruction, the execution of that in struction is stopped and is resumed following completion of interrupt servicing). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only w hen an interrupt occurs before stack pointer update) nextpc: the pc value at which processing is st arted following interrupt/exception processing. 2. the execution address of the illegal opcode when an illegal opcode exception occurs is calculated with (restored pc ? 4).
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 479 17.2 non-maskable interrupts non-maskable interrupt request signals are acknowledged unconditionally, even when interrupts are disabled (di state). non-maskable interrupts (nmi) are not subject to pr iority control and take precedence over all other interrupt request signals. the following three types of non-maskable interrupt request signals are available in the v850es/ke1. ? ? ?
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 480 figure 17-1. acknowledging non-maskab le interrupt request signals (1/2) (a) if two or more nmi request si gnals are simultan eously generated main routine system reset nmi, intwdt2 request
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 481 figure 17-1. acknowledging non-maskab le interrupt request signals (2/2) (b) if a new non-maskable interr upt request signal is generated during a non-maskable interrupt servicing non-maskable interrupt currently being serviced non-maskable interrupt request newly generated during non-maskable interrupt servicing nmi intwdt1 intwdt2 nmi generation of nmi request during nmi processing generation of intwdt1 request during nmi processing (np = 1 state prior to intwdt1 request is maintained) generation of intwdt1 request during nmi processing (set np = 0 before intwdt1 request) generation of intwdt1 request during nmi processing (set np = 0 after intwdt1 request) generation of intwdt2 request during nmi processing main routine nmi request
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 482 17.2.1 operation upon generation of a non-maskable interrupt request si gnal, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes the exception code (0010h, 0020h, 0030h ) to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. <5> loads the handler address (00000010h, 00000020h, 00000030h) of the non-maskable interrupt to the pc and transfers control. figure 17-2 shows the servicing flow for non-maskable interrupts. figure 17-2. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request held pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 handler address intc acknowledged cpu processing psw. np 1 0
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 483 17.2.2 restore execution is restored from non-maskable inte rrupt servicing by the reti instruction. (1) in case of nmi restore from nmi processing is done with the reti instruction. when the reti instruction is executed , the cpu performs the following processing and transfers control to the address of the restored pc. (i) loads the values of the restored pc and psw from fepc and fepsw , respectively, because the psw.ep bit and the psw.np bit are 0 and 1, respectively. (ii) transfers control back to the load ed address of the restored pc and psw. figure 17-3 shows the processing fl ow of the reti instruction. figure 17-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep bit and the np bit are changed by the ldsr instruction dur ing non-maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and set the np bit back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. (2) in case of intwdt1, intwdt2 signals for non-maskable interrupt servicing by the non-maskabl e interrupt request signals (intwdt1, intwdt2), refer to 17.10 cautions .
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 484 17.2.3 np flag the np flag is a status flag that indicates that non-maskable in terrupt servicing is in progress. this flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt serving in progress np 0 1 nmi servicing status after reset: 00000020h
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 485 17.3 maskable interrupts maskable interrupt request signals can be masked by interr upt control registers. the v850es/ke1 has 30 or 31 maskable interrupt sources (refer to 17.1.1 features ). if two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. in addition to the default pr iority, eight levels of interrupt priorities can be specified by using the interrupt control registers, allowing programmable priority control. when an interrupt request signal has been acknowledged, the interrupt disabled (di) status is set and the acknowledgment of other maskable inte rrupt request signals is disabled. when the ei instruction is executed in an interrupt servicing routine, the interr upt enabled (ei) status is set, which enables acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal currently in progress. note that only interrupt request signals with a higher priority have this capability; interrupt request signals with the same priority level cannot be nested. to use multiple interrupts, it is neces sary to save eipc and eipsw to memory or a register befor e executing the ei instruction, and restore eipc and eipsw to the original values by executing the di instruction before the reti instruction. when the wdtm1.wdtm14 bit is cleared to 0, the watchdog timer 1 overflow interrupt functions as a maskable interrupt (intwdtm1). 17.3.1 operation if a maskable interrupt request signal is generated, t he cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to t he lower halfword of ecr (eicc). <4> sets the psw.id bit to 1 and clears the psw.ep bit to 0. <5> loads the corresponding handler addr ess to the pc and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal that occurs while another interrupt is being serviced (when psw.np bit = 1 or id bit = 1) are held pending internally. when the interrupts are unmasked, or when the np bit = 0 and the id bit = 0 by using the reti and ldsr instructions, a new maskable interrupt servicing is started in accordance with th e priority of the pending maskable interrupt request signal. figure 17-4 shows the servicing flow for maskable interrupts.
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 486 figure 17-4. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id ispr. corresponding- bit note pc intc acknowledged cpu processing interrupt mask released? priority higher than that of interrupt currently being serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt requests? highest default priority of interrupt requests with the same priority? restored pc psw exception code 0 1 1 handler address note for the ispr register, refer to 17.3.6 in-service prio rity register (ispr) .
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 487 17.3.2 restore execution is restored from maskable interrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. (1) loads the values of the restored pc and psw fr om eipc and eipsw because the psw.ep bit and the psw.np bit are both 0. (2) transfers control to the loaded address of the restored pc and psw. figure 17-5 shows the processing fl ow of the reti instruction. figure 17-5. reti instruction processing reti instruction original processing restored pc psw ispr. corresponding -bit note eipc eipsw 0 psw. ep 1 0 1 0 pc psw fepc fepsw psw. np note for the ispr register, refer to 17.3.6 in-service prio rity register (ispr) . caution when the ep bit and the np bit are ch anged by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and the np bit back to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow.
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 488 17.3.3 priorities of maskable interrupts intc provides a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority leve l control: control based on the default pr iority levels, and control based on the programmable priority levels specified by the interrupt priority level specificat ion bit (xxicn.xxprn bit). when two or more interrupts having the same priority level specifi ed by xxprn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request (default priority level) beforehand. for more information, refer to table 17-1 interrupt source list . programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request signal is acknowledged , the psw.id flag is automatically set (1). therefore, when multiple interrupts are to be used, clear (0) the id flag bef orehand (for example, by plac ing the ei instruction into the interrupt service program) to enable interrupts. remark xx: identifying name of eac h peripheral unit (refer to table 17-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 17-2 interrupt control registers (xxicn) )
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 489 figure 17-6. example of interrupt nesting (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the re lative priority between two interrupt request signals.
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 490 figure 17-6. example of interrupt nesting (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 491 figure 17-7. example of servicing simultan eously generated inte rrupt request signals main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b servicing of interrupt request c servicing of interrupt request a interrupt requests b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. notes 1. higher default priority 2. lower default priority
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 492 17.3.4 interrupt control register (xxlcn) an interrupt control register is assigned to each maska ble interrupt and sets the control conditions for each maskable interrupt request. the interrupt control regist ers can be read or written in 8-bit or 1-bit units. after reset, xxicn is set to 47h. caution be sure to read the xxicn. xxifn bit while interrupts are disabled (d i). if the xxifn bit is read while interrupts are enabled (e i), an incorrect value may be read if there is a conflict between acknowledgment of the interrupt and reading of the bit. xxifn interrupt request not generated interrupt request generated xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 enables interrupt servicing disables interrupt servicing (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest) specifies level 1 specifies level 2 specifies level 3 specifies level 4 specifies level 5 specifies level 6 specifies level 7 (lowest) xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff168h < > < > note automatically reset by hardware when interrupt request is acknowledged. remark xx: identifying name of eac h peripheral unit (refer to table 17-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 17-2 interrupt control registers (xxicn) ) following tables list the addresses and bits of the interrupt control registers.
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 493 table 17-2. interrupt c ontrol registers (xxlcn) bits address register <7> <6> 5 4 3 2 1 0 fffff110h wdt1ic wdt1if wdt1mk 0 0 0 wdt1pr2 wdt1pr1 wdt1pr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff124h tm0ic10 tm0if10 tm0mk10 0 0 0 tm0pr102 tm0pr101 tm0pr100 fffff126h tm0ic11 tm0if11 tm0mk11 0 0 0 tm0pr112 tm0pr111 tm0pr110 fffff128h tm5ic0 tm5if0 tm5mk0 0 0 0 tm5pr02 tm5pr01 tm5pr00 fffff12ah tm5ic1 tm5if1 tm5mk1 0 0 0 tm5pr12 tm5pr11 tm5pr10 fffff12ch csi0ic0 csi0if0 csi0mk0 0 0 0 csi0pr02 csi0pr01 csi0pr00 fffff12eh csi0ic1 csi0if1 csi0mk1 0 0 0 csi0pr12 csi0pr11 csi0pr10 fffff130h sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff132h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff138h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff13ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff13ch tmhic0 tmhif0 tmhmk0 0 0 0 tmhpr02 tmhpr01 tmhpr00 fffff13eh tmhic1 tmhif1 tmhmk1 0 0 0 tmhpr12 tmhpr11 tmhpr10 fffff142h iicic0 note iicif0 iicmk0 0 0 0 iicpr02 iicpr01 iicpr00 fffff144h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff146h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff148h wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff14ah wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff14ch brgic brgif brgmk 0 0 0 brgpr2 brgpr1 brgpr0 fffff174h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff176h tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccpr02 tp0ccpr01 tp0ccpr00 fffff178h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10 note only in the
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 494 17.3.5 interrupt mask registers 0, 1, 3 (imr0, imr1, imr3) these registers set the interrupt mask status for maskable interrupts. the xxmkn bit of the imr0, imr1, and imr3 registers and the xxmkn bit of the xxlcn register are respectively linked. the imrm register can be read or wri tten in 16-bit units (m = 0, 1, 3). when the higher 8 bits of the imrk r egister are treated as the imrkh register and the lower 8 bits of the imrk register as the imrkl register, they can be read or written in 8-bit or 1-bit units (k = 0, 1). caution in the device file, th e xxmkn bit of the xxicn register is de fined as a reserved word. therefore, if bit manipulation is performed using the name xxm kn, the xxicn register, not the imrm register, is rewritten (as a result, the imrm register is also rewritten). csi0mk1 pmk6 imr0 (imr0h note ) (imr0l) csi0mk0 pmk5 tm5mk1 pmk4 tm5mk0 pmk3 tm0mk11 pmk2 tm0mk10 pmk1 1 pmk0 1 wdt1mk after reset: ffffh r/w address: imr0 fffff100h, imr0l fffff100h, imr0h fffff101h after reset: ffffh r/w address: imr1 fffff102h, imr1l fffff102h, imr1h fffff103h 1 tmhmk1 imr1 (imr1h note ) (imr1l) brgmk tmhmk0 wtmk stmk1 wtimk srmk1 krmk sremk1 admk stmk0 iicmk0 srmk0 1 sremk0 xxmkn 0 1 enables interrupt servicing disables interrupt servicing 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 interrupt mask flag setting after reset: ffffh r/w address: imr3, imr3l fffff106h 1 1 imr3 (imr3l) 1 1 1 1 1 tp0ccmk1 1 tp0ccmk0 1 tp0ovmk 1 1 1 1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 note when reading from or writing to bits 8 to 15 of the imr0 and imr1 registers in 8-bit or 1- bit units, specify these bits as bits 0 to 7 of the imr0h and imr1h registers. caution set bits 9 and 8 of the imr0 register, bits 15 and 8 of the imr1 register, and bits 15 to 5, 1, and 0 of the imr3 register to 1. the operation is not guaranteed if their value is changed. remark xx: identifying name of eac h peripheral unit (refer to table 17-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 17-2 interrupt control registers (xxicn) )
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 495 17.3.6 in-service priority register (ispr) this register holds the priority level of the maskable in terrupt currently being ackno wledged. when the interrupt request signal is acknowledged, the bit of this register corres ponding to the priority level of that interrupt request signal is set (1) and remains set while the interrupt is being serviced. when the reti instruction is executed, t he bit among those that are set (1) in t he ispr register that corresponds to the interrupt request signal having the highest priority is aut omatically cleared (0) by hardw are. however, it is not cleared (0) when execution is returned from non-maskab le interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. after reset, ispr is cleared to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after th e bits of the register have been set to 1 by acknowledging the interrupt may be read. to accura tely read the value of the ispr register before an interrupt is acknowledge d, read the register while inte rrupts are disabled (di status). ispr7 interrupt request with priority n is not acknowledged interrupt request with priority n is being acknowledged isprn 0 1 priority of interrupt currently being acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah < > < > < > < > < > < > < > < > remark n = 0 to 7 (priority level)
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 496 17.3.7 id flag the interrupt disable flag (id) is allocated to the psw and controls the maskable inte rrupt?s operating state, and stores control information regarding enabling/disa bling reception of interrupt request signals. after reset, this flag is set to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled id 0 1 maskable interrupt servicing specification note after reset: 00000020h note interrupt disable flag (id) function id is set (1) by the di instruction and cleared (0) by the ei instruction. its value is also modified by the reti instruction or ld sr instruction when referencing the psw. non-maskable interrupt request signals and e xceptions are acknowledged regardless of this flag. when a maskable interrupt reques t signal is acknowledged, the id flag is automatically set (1) by hardware. an interrupt request signal generated during t he acknowledgment disabled period (id flag = 1) can be acknowledged when the xxicn.xxifn bit is set (1), and the id flag is cleared (0).
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 497 17.3.8 watchdog timer mode register 1 (wdtm1) this register is a special register that can be written to only in a s pecial sequence. to generate a maskable interrupt (intwdt1), clear the wdtm14 bit to 0. this register can be read or written in 8- bit or 1-bit units (for details, refer to chapter 11 watchdog timer functions ). run1 stop count operation clear counter and start count operation run1 0 1 watchdog timer operation mode selection note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (generate maskable interrupt intwdtm1 when overflow occurs) watchdog timer mode 1 note 3 (generate non-maskable interrupt intwdt1 when overflow occurs) watchdog timer mode 2 (start wdtres2 reset operation when overflow occurs) wdtm14 0 0 1 1 wdtm13 0 1 0 1 watchdog timer operation mode selection note 2 < > notes 1. once the run1 bit has been set (1), it cannot be cleared (0) by software. therefore, once counting starts, it cannot be stopped except by reset. 2. once the wdtm14 and wdtm13 bits have bee n set (1), they cannot be cleared (0) by software. reset is the only way to clear these bits. 3. for non-maskable interrupt servicing due to a non-maskable interrupt request signal (intwdt1), refer to 17.10 cautions .
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 498 17.4 external interrupt request i nput pins (nmi, intp0 to intp6) 17.4.1 noise elimination (1) noise elimination for nmi pin the nmi pin includes a noise eliminator that operates using analog delay. therefore, a signal input to the nmi pin is not detected as an edge unless it maintains its input level for a cert ain period. the edge is detected only after a certain period has elapsed. the nmi pin is used for releasing the stop mode. in the stop mode, noise elim ination using the system clock is not performed because the internal system clock is stopped. (2) noise elimination for intp0 to intp6 pins the intp0 to intp6 pins include a noise eliminator that operates using analog del ay. therefore, a signal input to each pin is not detected as an edge unless it main tains its input level for a certain period. the edge is detected only after a certain period has elapsed. 17.4.2 edge detection the valid edges of the nmi and intp0 to intp6 pins can be selected from the following four types for each pin. ? ? ? ?
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 499 (1) external interrupt rising and falling e dge specification registers 0 (intr0, intf0) these are 8-bit registers t hat specify detection of the rising and fa lling edges of the nmi and intp0 to intp3 pins. these registers can be read or wri tten in 8-bit or 1-bit units. after reset, these registers are cleared to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf0n and intr0n bits = 00. 0 intr0 intr06 intr05 intr04 intr03 intr02 intp2 intp1 intp0 nmi 00 after reset: 00h r/w address: intr0 fffffc20h, intf0 fffffc00h intp2 intp1 intp0 nmi intp3 intp3 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 remark for specification of the valid edge, refer to table 17-3 . table 17-3. nmi and intp0 to in tp3 pins valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 500 (2) external interrupt rising and falling edge specification registers 9h (intr9h, intf9h) these are 8-bit registers that s pecify detection of the rising edge of the intp4 to intp6 pins. these registers can be read or wri tten in 8-bit or 1-bit units. after reset, these registers are cleared to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf9n and intr9n bits = 00. intr915 intr9h intr914 intr913 0 0 0 0 0 after reset: 00h r/w address: intr9h fffffc33h, intf9h fffffc13h intp5 intp4 intp6 intp5 intp4 intp6 intf915 intf9h intf914 intf913 0 0 0 0 0 remark for specification of the valid edge, refer to table 17-4 . table 17-4. intp4 to intp6 pins valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 13 to 15: control of intp4 to intp6 pins
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 501 17.5 software exceptions a software exception is generated when the cpu executes the trap instruction. software exceptions can always be acknowledged. 17.5.1 operation if a software exception occurs, the cpu performs the fo llowing processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1. <5> loads the handler address (00000040h or 00000050h) for the software exception routine to the pc and transfers control. figure 17-8 shows the software exception processing flow. figure 17-8. software exception processing trap instruction note eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note trap instruction format: trap vector (however, vector = 00h to 1fh) the handler address is determined by the operand (vector) of the trap instructio n. if the vector is 00h to 1fh, the handler address is 00000040h, and if the vector is 10h to 1fh, the handler address is 00000050h.
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 502 17.5.2 restore execution is restored from software exceptio n processing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. figure 17-9 shows the processing fl ow of the reti instruction. figure 17-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep bit and the np bit are ch anged by the ldsr instruction during software exception processing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessa ry to set the psw.ep bit back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow.
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 503 17.5.3 ep flag the ep flag, which is bit 6 of the psw, is a status flag that indicate s that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress exception processing in progress ep 0 1 exception processing status after reset: 00000020h
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 504 17.6 exception trap the exception trap is an interrupt that is requested when t he illegal execution of an instruction takes place. in the v850es/ke1, an illegal opcode trap (ilgop) is considered as an exception trap. 17.6.1 illegal opcode an illegal opcode is defined as an instruction with instru ction opcode (bits 10 to 5) = 111111b, sub-opcode (bits 26 to 23) = 0111b to 1111b, and sub-opcode (bit 16) = 0b. when such an instruction is ex ecuted, an exception trap is generated. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 x: don?t care caution it is recommended not to use illegal opcode because instructi ons may newly be assigned in the future. (1) operation upon generation of an exception trap, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits. <4> loads the handler address (00000060h) for the except ion trap routine to the pc and transfers control. figure 17-10 shows the exception trap processing flow.
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 505 figure 17-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore execution is restored from exception trap processing by the dbret instruction. when the dbret instruction is executed, the cpu performs the fo llowing processing and transfers cont rol to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. figure 17-11 shows the processing flow for re store from exception trap processing. figure 17-11. processing flow fo r restore from exception trap dbret instruction pc psw dbpc dbpsw jump to restored pc address
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 506 17.6.2 debug trap a debug trap is an exception that occurs upon execution of the dbtrap inst ruction and that can be acknowledged at all times. when a debug trap occurs, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) for the debug trap routine to the pc and transfers control. figure 17-12 shows the debug trap processing flow. figure 17-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 507 (2) restore execution is restored from debug trap pr ocessing by the dbret instruction. when the dbret instruction is executed, the cpu performs the following processing and tr ansfers control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. figure 17-13 shows the processing flow fo r restore from debug trap processing. figure 17-13. processing flow for restore from debug trap dbret instruction pc psw dbpc dbpsw jump to restored pc address
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 508 17.7 multiple interru pt servicing control multiple interrupt servicing control is a function that st ops an interrupt service routine currently in progress if a higher priority interrupt request signal is generated, and processes the acknowledgm ent operation of the higher priority interrupt request signal. if an interrupt request signal with a lower or equal priority is generated and a service routi ne is currently in progress, the later interrupt request signal will be held pending. multiple interrupt servicing control is performed when inte rrupts are enabled (psw.id bit = 0). even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (id bit = 0). if a maskable interrupt or software exception is generated in a maskable interrupt or software exception service program, eipc and eipsw must be saved. the following example illustrates the procedure. (1) to acknowledge maskable interrupt re quest signals in service program service program for maskable interrupt or exception ? ? ? ? ? ? ? ? ?
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 509 (2) to generate exception in service program service program for maskable interrupt or exception ? ? ? ? ? ? ? ?
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 510 17.8 interrupt response time except in the following cases, the cpu interrupt response ti me is a minimum of 4 clocks. if inputting consecutive interrupt request signals, at least 4 clocks must be placed between each interrupt request signal. ? ? ? ? ? ? ? ? ? ?
chapter 17 interrupt/exception processing function preliminary user?s manual u16892ej1v0ud 511 17.9 periods in which interrupts are not acknowledged by cpu interrupts are acknowledged by the cpu while an instru ction is being executed. however, no interrupt is acknowledged between an interrupt request non-sample instru ction and the next instru ction (interrupts are held pending). the following instructions are interrupt request non-sample instructions. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instructions (vs. psw) ? store instruction for the prcmd register ? store instruction and set1, not1, and clr1 instructions for the following registers ? interrupt-related registers: interrupt control register (xxlcn), interrupt mask registers 0, 1, 3 (imr0, imr1, imr3) ? power save control register (psc) 17.10 cautions design the system so that restoring by the reti instructi on is as follows after a non-maskable interrupt triggered by a non-maskable interrupt request signal (intwdt1/intwdt2) is serviced. figure 17-15. restoring by reti instruction generation of intwdt1/intwdt2 intwdt1/intwdt2 servicing routine software reset processing routine fepc software reset processing address fepsw value so that np bit = 1, ep bit = 1 reti ten reti instructions (fepc and fepsw must be set) psw initial set value of psw initialization processing
preliminary user?s manual u16892ej1v0ud 512 chapter 18 key interrupt function 18.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the krm register. caution if any of the kr0 to kr7 pins is at low l evel, the intkr signal is not generated even if a falling edge is input to another pin. table 18-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 18-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
chapter 18 key interrupt function preliminary user?s manual u16892ej1v0ud 513 18.2 register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or writt en in 8-bit or 1-bit units. after reset, krm is cleared to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 key return mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution if the krm register is changed, an interrupt request signal (intkr) may be generated. to prevent this, change th e krm register after disabling interrupts (di), and then enable interrupts (ei) a fter clearing the interrupt request flag (kric.krif bit) to 0. remark for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions .
preliminary user?s manual u16892ej1v0ud 514 chapter 19 standby function 19.1 overview the power consumption of the system can be effectively reduced by using t he standby modes in combination and selecting the appropriate mode for the application. the available standby modes are listed in table 19-1. table 19-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the operations of the internal circuits except the oscillator note 1 stop mode mode to stop all the operations of the internal circuits except the subclock oscillator note 2 subclock operation mode mode to use the subclock as the internal system clock sub-idle mode mode to stop all the operations of the internal circuits, except the oscillator, in the subclock operation mode notes 1. the pll does not stop. to realize low power consum ption, stop the pll and then shift to the idle mode. 2. change to the clock-through mode, stop the pll, t hen shift to the stop mode. for details, refer to chapter 5 clock generation function .
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 515 figure 19-1. status transition (1/2) normal operation mode (operation with main clock) wait for stabilization of oscillation wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count end of oscillation stabilization time count end of oscillation stabilization time count setting of halt mode interrupt request note 3 setting of stop mode idle mode halt mode stop mode reset note 5 interrupt request note 2 setting of idle mode interrupt request note 4 reset note 1 reset note 5 notes 1. reset by reset pin input, watchdog timer 1 overflow (wdtres1), or watchdog timer 2 overflow (wdtres2). 2. non-maskable interrupt request signal (nmi, intw dt1, intwdt2) or unmasked maskable interrupt request signal. 3. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp6 pin input), or unmasked internal interrupt request signal from peripheral functions operable in idle mode. 4. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp6 pin input), or unmasked internal interrupt request signal from peripheral functions operable in stop mode. 5. reset by reset pin input or watchdog timer 2 (when the cpu is operating on the subclock) overflow (wdtres2).
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 516 figure 19-1. status transition (2/2) normal operation mode (operation with main clock) subclock operation mode (operation with subclock) wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count setting of subclock operation mode setting of normal operation mode end of oscillation stabilization time count sub-idle mode reset note 1 interrupt request note 2 setting of idle mode reset note 1 notes 1. reset by reset pin input or watchdog timer 2 overflow (wdtres2). 2. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp6 pin input), or unmasked internal interrupt request signal from peripheral functions operable in sub-idle mode.
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 517 19.2 registers (1) power save control register (psc) this is an 8-bit register that controls the standby function. the stp bit of this register is used to specify the standby mode. the psc register is a special register that can be written to only in a special sequence (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. after reset, psc is cleared to 00h. nmi2m psc 0 nmi0m intm 0 0 stp 0 releasing standby mode note by intwdt2 signal enabled releasing standby mode note by intwdt2 signal disabled nmi2m 0 1 control of releasing standby mode note by intwdt2 signal releasing standby mode note by nmi pin input enabled releasing standby mode note by nmi pin input disabled nmi0m 0 1 control of releasing standby mode note by nmi pin input releasing standby mode note by maskable interrupt request signals enabled releasing standby mode note by maskable interrupt request signals disabled intm 0 1 control of releasing standby mode note by maskable interrupt request signals normal mode standby mode note stp 0 1 standby mode note setting after reset: 00h r/w address: fffff1feh < > < > < > < > note in this case, standby mode means the idle/s top mode; it does not in clude the halt mode. cautions 1. if the nmi2m, nmi0m, and intm bits, and the stp bit are set to 1 at the same time, the setting of nmi2m, nmi0m, and intm bits b ecomes invalid. if th ere is an unmasked interrupt request signal being held pending when the idle/stop mode is set, set the bit corresponding to the interrupt request signal (n mi2m, nmi0m, or intm) to 1, and then set the stp bit to 1. 2. when the idle/stop mode is set, set the psmr.psm bit and then set the stp bit.
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 518 (2) power save mode register (psmr) this is an 8-bit register that cont rols the operation status in the st andby mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. after reset, psmr is cleared to 00h. xtstp subclock oscillator used subclock oscillator not used xtstp 0 1 specification of subclock oscillator use psmr 0 0 0 0 0 0 psm idle mode stop mode psm 0 1 specification of operation in standby mode after reset: 00h r/w address: fffff820h < > cautions 1. be sure to clear the xtstp bi t to 0 during subclock resonator connection. 2. be sure to clear bits 1 to 6 of the psmr register to 0. 3. the psm bit is valid only when the psc.stp bit is 1.
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 519 (3) oscillation stabilization time selection register (osts) the wait time until the oscill ation stabilizes after the stop mode is releas ed is controlled by the osts register. the osts register can be read or written in 8-bit units. after reset, osts is set to 01h. 0 osts 0 0 0 0 osts2 osts1 osts0 2 13 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 19 /f x 2 20 /f x 2 21 /f x osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 5 mhz 10 mhz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 4 mhz 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms f x after reset: 01h r/w address: fffff6c0h cautions 1. the wait time following release of the stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the stop mode, regardless of whether the stop mode is released by re set or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to 0. 3. the oscillation stabilization ti me following reset release is 2 15 /f x (because the initial value of the osts register = 01h). 4. the oscillation stabilization time is also inserted during external clock input. remark f x : main clock oscillation frequency
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 520 19.3 halt mode 19.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock s upply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 19-3 shows the operation status in the halt mode. the average power consumption of the system can be reduc ed by using the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed with an unmasked interrupt request signal held pending, the system shifts to the halt mode, but the halt mode is immediately released by the pending interrupt request signal. 19.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt1, intwdt2 signal), an unmasked maskable interrupt request signal, and reset signal (reset pin input, wdtres1, wdtres2 signal). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interr upt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the halt mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the halt mode is released and that interrupt request signal is acknowledged. table 19-2. operation after releasing halt mode by interr upt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing halt mode by reset the same operation as the normal reset operation is performed.
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 521 table 19-3. operation status in halt mode when cpu is operating with main clock setting of halt mode item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation enabled subclock oscillator ?
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 522 19.4 idle mode 19.4.1 setting and operation status the idle mode is set by clearing the psmr.psm bit to 0 and setting the psc.stp bit to 1 in the normal operation mode. in the idle mode, the clock oscillator continues operati on but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on -chip peripheral functions that can operate with the subclock or an external clock continue operating. table 19-5 shows the operation status in the idle mode. the idle mode can reduce the power consumption more than the halt m ode because it stops the operation of the on-chip peripheral functions. the main clock oscill ator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the idle mode. 19.4.2 releasing idle mode the idle mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external inte rrupt request signal (intp0 to intp6 pin input), unmasked internal interrupt request signal from the peripheral function s operable in the idle mode, or reset (reset pin input, wdtres2 signal (when the cpu is operating on the subclock)). after the idle mode has been released, th e normal operation mode is restored. (1) releasing idle mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the idle mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interr upt request. if the idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the idle mode is released and that interrupt request signal is acknowledged. table 19-4. operation after releasing id le mode by interr upt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 523 (2) releasing idle mode by reset the same operation as the normal reset operation is performed. table 19-5. operation status in idle mode when cpu is operating with main clock setting of idle mode item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation enabled subclock oscillator ? ? ?
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 524 19.5 stop mode 19.5.1 setting and operation status the stop mode is set when the psmr.psm bit is set to 1 and the psc.stp bit is set to 1 in the normal operation mode. in the stop mode, the subclock oscillat or continues operating but the main cl ock oscillator stops. clock supply to the cpu and the on-chip peri pheral functions is stopped. as a result, program execution is st opped, and the contents of the inter nal ram before the stop mode was set are retained. the cpu and other on-ch ip peripheral functions stop operating. however, the on-chip peripheral functions that can operate with t he subclock oscillator or an exte rnal clock continue operating. table 19-7 shows the operation status in the stop mode. because the stop mode stops operation of the main clock oscillator, it reduc es the power consumption to a level lower than the idle mode. if the subclock oscillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the stop mode. 19.5.2 releasing stop mode the stop mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external inte rrupt request signal (intp0 to intp6 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the stop mode, or reset (reset pin input, wdtres2 signal (when the cpu is operating on the subclock)). after the stop mode has been released, the normal operat ion mode is restored after the oscillation stabilization time has been secured. (1) releasing stop mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interr upt request. if the stop mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the stop mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the stop mode is released and that interrupt request signal is acknowledged. table 19-6. operation after releasing st op mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing stop mode by reset the same operation as the normal reset operation is performed.
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 525 table 19-7. operation status in stop mode when cpu is operating with main clock setting of stop mode item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation stops subclock oscillator ?
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 526 19.5.3 securing oscillation stabilization time when stop mode is released when the stop mode is released, only the oscillation stabilization time set by the osts register elapses. if the stop mode has been released by reset, however, the reset value of the osts register, 2 15 /f x (8.192 ms at f x = 4 mhz) elapses. the operation performed when the stop mode is releas ed by an interrupt request signal is shown below. figure 19-2. oscillation stabilization time oscillated waveform main clock oscillator stops oscillation stabilization time count main clock stop mode status interrupt request caution for details of the osts register, refer to 19.2 (3) oscillation stabilization time selection register (osts).
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 527 19.6 subclock operation mode 19.6.1 setting and operation status the subclock operation mode is set when the pcc.ck3 bit is set to 1 in the normal operation mode. when the subclock operation mode is set, t he internal system clock is changed from the main clock to the subclock. when the pcc.mck bit is set to 1, the op eration of the main clock oscillator is stopped. as a result, the system operates only with the subclock. table 19-8 shows the operation stat us in subclock operation mode. in the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. in addition, the power consumption can be further reduced to the level of the stop mode by st opping the operation of t he main clock oscillator. cautions 1. when manipulating the ck3 bit, do no t change the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to ma nipulate the bit is recommended). for details, refer to 5.3 (1) processor cl ock control register (pcc). 2. if the following conditions are not satisfied, change the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. main clock (f xx ) > subclock (f xt : 32.768 khz)
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 528 table 19-8. operation status in subclock operation mode operation status setting of subclock operation item mode when main clock is oscillati ng when main clock is stopped cpu operable rom correction operable subclock oscillator oscillation enabled interrupt controller operable timer p (tmp0) operable stops operation 16-bit timer (tm01) operable operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) operable ? ?
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 529 19.7 sub-idle mode 19.7.1 setting and operation status the sub-idle mode is set when the psmr.psm bit is cleared to 0 and the psc.stp bit is set to 1 in the subclock operation mode. in this mode, the clock oscillator continues operation bu t clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is st opped and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and t he other on-chip peripheral functions are st opped. however, the on-chip peripheral functions that can operate with the subclock or an extern al clock continue operating. table 19-10 shows the operation status in the sub-idle mode. because the sub-idle mode stops oper ation of the cpu and other on-chip per ipheral functions, it can reduce the power consumption more than the subc lock operation mode. if the sub-idle mode is set after the main clock has been stopped, the power consumption can be reduced to a level as lo w as that in the stop mode. 19.7.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external interrupt request signal (intp0 to intp6 pin input), unmasked internal interrupt request signal from the peri pheral functions operable in the sub-idle mode, or reset (reset pin input, wdtres2 signal (when t he cpu is operating on the subclock)). when the sub-idle mode is released by an interrupt requ est signal, the subclock operation mode is set. if it is released by reset, the normal operation mode is restored. (1) releasing sub-idle m ode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of t he interrupt request. if the sub-idle mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the sub-idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-idle mode is released and that interrupt request signal is acknowledged. table 19-9. operation after releasing sub- idle mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing sub-id le mode by reset the same operation as the normal reset operation is performed.
chapter 19 standby function preliminary user?s manual u16892ej1v0ud 530 table 19-10. operation status in sub-idle mode operation status setting of sub-idle item mode when main clock is oscillati ng when main clock is stopped cpu stops operation rom correction stops operation subclock oscillator oscillation enabled interrupt controller stops operation timer p (tmp0) stops operation 16-bit timer (tm01) operable when intwt is selected as count clock operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) ? operable when ti5n is selected as count clock ? operable when inttm010 is selected as count clock and intwt is selected as count clock of tm01 ? operable when ti5n is selected as count clock ? operable when inttm010 is selected as count clock and when tm01 is enabled in sub-idle mode timer h (tmh0) stops operation timer h (tmh1) operable when f xt is selected as count clock watch timer stops operation operable when f xt is selected as count clock watchdog timer 1 operable stops operation watchdog timer 2 operable when f xt is selected as count clock csi00, csi01 stops operation oper able when sck0n input clock is selected as operation clock i 2 c0 note stops operation uart0 operable when asck0 is selected as count clock serial interface uart1 stops operation key interrupt function operable a/d converter stops operation real-time output operable when inttm5n is selected as real-time output trigger and ti5n is selected as count clock of tm5n port function retains status before sub-idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set. note only in the pd703207y, 70f3207hy remark n = 0, 1
preliminary user?s manual u16892ej1v0ud 531 chapter 20 reset function 20.1 overview the following reset functions are available. ? ? ?
chapter 20 reset function preliminary user?s manual u16892ej1v0ud 532 20.3 operation the system is reset, initializing each hardware unit, when a lo w level is input to the reset pin or if watchdog timer 1 or watchdog timer 2 overflows (wdtres1 or wdtres2). while a low level is being input to the reset pin, the ma in clock oscillator stops. t herefore, the overall power consumption of the system can be reduced. if the reset pin goes high or if the wdtres1 or wdtres2 signal is received, the reset status is released. if the reset status is released by reset pin input or the wdtres2 signal, the oscillation stabilization time elapses (reset value of osts register: 2 15 /f xx ) and then the cpu starts program execution. if the reset status is released by the wdtres1 signal, t he oscillation stabilization ti me is not inserted because the main clock oscillator does not stop.
chapter 20 reset function preliminary user?s manual u16892ej1v0ud 533 table 20-1. hardware status on reset pi n input or occurrence of wdtres2 signal item during reset after reset main clock oscillator (f x ) oscillation stops (f x = 0 level) oscillation starts subclock oscillator (f xt ) oscillation can continue without effect from reset note 1 peripheral clock (f xx to f xx /1024), internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts. however, operation stops during oscillation stabilization time count. watchdog timer 1 clock (f xw ) operation stops operation starts note 2 internal ram undefined if power-on reset occurs or wr iting data to ram and reset conflict (data loss); otherwise, retain s values immediatel y before reset input. i/o lines (ports) high impedance on-chip peripheral i/o registers initialized to specified status other on-chip peripheral fu nctions operation stops o peration can be started notes 1. the on-chip feedback resistor is ?connected? by default (refer to 5.3 (1) processor clock control register (pcc) ). 2. the clock is in the initializ ed status (interval timer mode). table 20-2. hardware status on occurrence of wdtres1 signal item during reset after reset main clock oscillator (f x ) oscillation continues note subclock oscillator (f xt ) oscillation can continue without effect from reset note peripheral clock (f xx to f xx /1024), internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts watchdog timer 1 clock (f xw ) operation continues internal ram undefined if writing data to ram and reset c onflict (data loss); otherwise, retains values immediately before reset input. i/o lines (ports) high impedance on-chip peripheral i/o registers initialized to specified status other on-chip peripheral fu nctions operation stops o peration can be started note the on-chip feedback resistor is ?connected? by default (refer to 5.3 (1) processor cl ock control register (pcc) ).
chapter 20 reset function preliminary user?s manual u16892ej1v0ud 534 figure 20-2. hardware status on reset pin input figure 20-3. operation on power application oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay reset f x v dd f clk oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay
preliminary user?s manual u16892ej1v0ud 535 chapter 21 rom correction function 21.1 overview the rom correction function is used to replace part of the program in the internal rom with the program of an external memory or the internal ram. by using this function, program bugs foun d in the internal rom can be corrected. up to four addresses can be specified for correction. figure 21-1. block diag ram of rom correction instruction address bus block replacing bug with dbtrap instruction instruction data bus rom dbtrap instruction generation block correction address register n (coradn) correction control register (corenn bit) comparator remark n = 0 to 3
chapter 21 rom correction function preliminary user?s manual u16892ej1v0ud 536 21.2 registers (1) correction address registers 0 to 3 (corad0 to corad3) these registers are used to set the firs t address of the program to be corrected. the program can be corrected at up to four places because four coradn registers are provided. the coradn register can be read or written in 32-bit units. if the higher 16 bits of the coradn re gister are used as the coradnh regi ster, and the lower 16 bits as the coradnl register, these registers can be read or written in 16-bit units. after reset, coradn is cleared to 00000000h. set correction addresses in the range of 0000000h to 001fffeh in the v850es/ke1. bits 0 and 20 to 31 are fixed to 0. after reset: 00000000h r/w address: corad0 fffff840h, corad0l fffff840h, corad0h fffff842h, corad1 fffff844h, corad1l fffff844h, corad1h fffff846h, corad2 fffff848h, corad2l fffff848h, corad2h fffff84ah, corad3 fffff84ch, corad3l fffff84ch, corad3h fffff84eh 17 16 20 correction address fixed to 0 note 0 coradn (n = 0 to 3) 31 19 1 0 note be sure to clear these bits to 0.
chapter 21 rom correction function preliminary user?s manual u16892ej1v0ud 537 (2) correction control register (corcn) this register disables or enables the correction oper ation at the address specifie d by the coradn register. each channel can be enabled or disabled by this register. this register can be read or written in 8-bit or 1-bit units. after reset, corcn is cleared to 00h. 0 disabled enabled corenn 0 1 correction operation enable/disable corcn 0 0 0 coren3 coren2 coren1 coren0 after reset: 00h r/w address: fffff880h < > < > < > < > remark n = 0 to 3 table 21-1. correspondence between corcn register bits and coradn registers corcn register bit corresponding coradn register coren3 corad3 coren2 corad2 coren1 corad1 coren0 corad0 21.3 rom correction operation and program flow <1> if the address to be corrected and the fetch address of t he internal rom match, the fetch code is replaced by the dbtrap instruction. <2> when the dbtrap instruction is execut ed, execution branches to address 00000060h. <3> software processing after branching causes the result of rom correction to be judged (the fetch address and rom correction operation are confirmed) and exec ution to branch to the correction software. <4> after the correction software has been executed, the return address is set, and return processing is started by the dbret instruction. cautions 1. the software that performs <3> and <4> must be executed in the internal rom/ram. 2. when setting an address to be corrected to the coradn register, clear the higher bits to 0 in accordance with the capacity of the internal rom. 3. the rom correction function cannot be used to correct the data of the internal rom. it can only be used to correct instructi on codes. if rom correction is u sed to correct data, that data is replaced with the dbtrap instruction code.
chapter 21 rom correction function preliminary user?s manual u16892ej1v0ud 538 figure 21-2. rom correction operation and program flow reset & start fetch address = coradn? coradn = dbpc ?
preliminary user?s manual u16892ej1v0ud 539 chapter 22 flash memory the following products are the flash memory vers ions (single power supply) of the v850es/ke1. caution there are differences in noise immunity a nd noise radiation between th e flash memory and mask rom versions. when pre-producing and applicati on set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluation for the commercial samples (not engineering samples) of the mask rom version. for the electrical specifications related to the flash memory rewriting, refer to chapter 23 electrical specifications (target). ? pd70f3207h, 70f3207hy: on-chip 128 kb flash memory flash memory versions are commonly used in the following development environments and mass production applications. { for altering software after the v850es/ ke1 is soldered onto the target system. { for data adjustment when starting mass production. { for differentiating software according to the specif ication in small scale production of various models. { for facilitating inventory management. { for updating software after shipment. 22.1 features { 4-byte/1-clock access (when instruction is fetched) { capacity: 128 kb { write voltage: erase/write with a single power supply { rewriting method ? rewriting by communication with dedicated flash pr ogrammer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { flash memory write prohibit f unction supported (security function) { safe rewriting of entire flash memory area by self programming using boot swap function { interrupts can be acknowledged during self programming. caution tm50 and tm51 (including interrupts in ttm50 and inttm51) cannot be used during self programming. for details , refer to 22.5.6 inte rnal resources used.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 540 22.2 memory configuration the 128 kb internal flash memory area is divided into 64 blocks and can be programmed/erased in block units. all the blocks can also be erased at once. when the boot swap function is used, the physical memory (blocks 0 to 3) located at the addresses of boot area 0 is replaced by the physical memory (blocks 4 to 7) locate d at the addresses of boot area 1. for details of the boot swap function, refer to 22.5 rewriting by self programming . figure 22-1. flash memory mapping block 0 (2 kb) block 1 (2 kb) block 2 (2 kb) block 3 (2 kb) block 5 (2 kb) block 6 (2 kb) block 7 (2 kb) block 8 (2 kb) block 4 (2 kb) block 63 (2 kb) 00007ffh 0000800h 0000fffh 0001000h 00027ffh 0002800h 0002fffh 0003000h 00037ffh 0003800h 0003fffh 0004000h 00047ffh 0004800h 001ffffh 0004fffh 0005000h 00017ffh 0001800h 0001fffh 0002000h 0000000h 3ffffffh 3ff0000h 3feffffh 3fff000h 3ffefffh 0020000h 001ffffh 0000000h use prohibited internal flash memory area (128 kb) boot area 0 note (8 kb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) boot area 1 note (8 kb) note boot area 0 (blocks 0 to 3): boot area boot area 1 (blocks 4 to 7): area used to replace boot area via boot swap function
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 541 22.3 functional outline the internal flash memory of the v850es/ke1 can be rewrit ten by using the rewrite f unction of the dedicated flash programmer, regardless of whether the v850es/ke1 has already been mounted on the target system or not (on- board/off-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programmi ng) is ideal for an application where it is assumed that the program is changed after production/sh ipment of the target syst em. a boot swap function t hat rewrites the entire flash memory area safely is also supported. in addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten und er various conditions, such as while communicating with an external device. table 22-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/off- board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance). normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 542 table 22-2. basic functions support ( { : supported, { { chip erasure the contents of the entire memory area are erased all at once. { { { verify/checksum data read from the flash memory is compared with data transferred from the flash programmer. { { { security setting use of the block erase command, chip erase command, and program command can be prohibited. { { : executable, { program command: { chip erase command prohibit execution of block erase and chip erase commands on all the blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. block erase command: { program command prohibit write and block erase commands on all the blocks are prohibited. setting of prohibition can be initialized by execution of the chip erase command. block erase command: { program command:
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 543 22.4 rewriting by dedicated flash programmer the flash memory can be rewritten by using a dedicat ed flash programmer after the v850es/ke1 is mounted on the target system (on-board pr ogramming). the flash memory can also be re written before the device is mounted on the target system (off-board progr amming) by using a dedicated program adapter (fa series). 22.4.1 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850es/ke1. figure 22-2. environment required for writing programs to flash memory host machine rs-232c dedicated flash programmer v850es/ke1 flmd1 v dd v ss reset uart0/csi00 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy s tat v e flmd0 usb a host machine is required for controlling the dedicated flash programmer. uart0 or csi00 is used for the interface between the dedicated flash programmer and the v850es/ke1 to perform writing, erasing, etc. a dedicated program adapter (fa series) is required for off-board writing. remark the fa series is a product of naito densei machida mfg. co., ltd.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 544 22.4.2 communication mode communication between the dedicated flash program mer and the v850es/ke1 is performed by serial communication using the uart0 or csi 00 interfaces of the v850es/ke1. (1) uart0 transfer rate: 9,600 to 153,600 bps figure 22-3. communication with dedicated flash programmer (uart0) dedicated flash programmer v850es/ke1 v dd v ss reset txd0 rxd0 flmd1 flmd1 flmd0 flmd0 v dd gnd reset rxd txd x1 x2 clk pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve (2) csi00 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 22-4. communication with de dicated flash programmer (csi00) dedicated flash programmer v850es/ke1 flmd1 v dd v ss reset so00 si00 sck00 flmd1 flmd0 flmd0 v dd gnd reset si so sck pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx y yy x x x x x x x x x x x x x x x xxxx y yyy statve x1 x2 clk
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 545 (3) csi00 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 22-5. communication with dedi cated flash programmer (csi00 + hs) dedicated flash programmer v850es/ke1 v dd v ss reset so00 si00 sck00 pcm0 v dd flmd1 flmd1 flmd0 flmd0 gnd reset si so sck hs pg-fp4 (flash p ro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve x1 x2 clk the dedicated flash programmer outputs the transfer clock, and the v850es/ke1 operates as a slave. when the pg-fp4 is used as the d edicated flash programmer, it gener ates the following signals to the v850es/ke1. for details, refer to the pg-fp4 user?s manual (u15260e) . table 22-4. signal connections of dedicated flash programmer (pg-fp4) pg-fp4 v850es/ke1 processing for connection signal name i/o pin function pin name uart0 csi00 csi00 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/ke1 x1, x2 note 2 note 2 note 2 reset output reset signal reset si/rxd input receive signal so00 so/txd output transmit signal si00 sck output transfer clock sck00 hs input handshake signal for csi00 + hs communication pcm0 notes 1. wire the pin as shown in figure 22-6, or connect it to gnd on board via a pull-down resistor. 2. connect these pins to supply a clock from the pg -fp4 (wire as shown in figure 22-6, or create an oscillator on board and supply the clock). remark : must be connected. : does not have to be connected.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 546 table 22-5. wiring between ? ?
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 547 figure 22-6. wiring example of v850es/ke1 flash writing adapter (fa-64gk-9et-a, fa-64gb-8eu-a) pd70f3207h, pd70f3207hy vdd gnd gnd vdd gnd vdd vdd gnd 32 connect to vdd. connect to gnd. 1 7 6 2 33 45 52 note 19 20 21 so sck si x1 /reset v pp reserve/hs x2 rfu-3 rfu-2 rfu-1 flmd1 flmd0 vde 89 4 3 note wire the flmd1 pin as shown in the figure, or c onnect it to gnd on board via a pull-down resistor. remarks 1. handle the pins not described above in accord ance with the specified handling of unused pins (refer to 2.2 pin i/o circuits and recomm ended connection of unused pins) . when connecting to v dd via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 64-pin plastic tqfp or 64-pin plastic lqfp (fine pitch) package. 3. this diagram shows the wiring when using a handshake-supporting csi.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 548 22.4.3 flash memory control the following shows the procedure for manipulating the flash memory. figure 22-7. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 549 22.4.4 selection of communication mode in the v850es/ke1, the communication mode is selected by inputting pulses (12 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. figure 22-8. selection of communication mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxd0 (input) txd0 (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released note the number of clocks is as follows depending on the communication mode. flmd0 pulse communication mode remarks 0 uart0 communication rate: 9600 bps (after reset), lsb first 8 csi00 v850es/ke1 performs slave operation, msb first 11 csi00 +
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 550 22.4.5 communication commands the v850es/ke1 communicates with the dedicated flash programmer by means of commands. the signals sent from the dedicated flash programmer to the v850es/ke1 are called ?commands?. the response signals sent from the v850es/ke1 to the dedicated flash programmer are called ?response commands?. figure 22-9. communication commands dedicated flash programmer v850es/ke1 command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve the following shows the commands for flash memory cont rol in the v850es/ke1. all of these commands are issued from the dedicated flash programmer, and the v850es/ke1 performs the processing corresponding to the commands. table 22-6. flash memory control commands support classification command name csi00 csi00 + hs uart0 function blank check block blank check command { { { checks if the contents of the memory in the specified block have been correctly erased. chip erase command { { { erases the contents of the entire memory. erase block erase command { { { erases the contents of the memory of the specified block. write write command { { { writes the specified address range, and executes a contents verify check. verify command { { { compares the contents of memory in the specified address range with data transferred from the flash programmer. verify checksum command { { { reads the checksum in the specified address range. silicon signature command { { { reads silicon signature information. system setting, control security setting command { { { disables the chip erase command, enables the block erase command, and disables the write command.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 551 22.4.6 pin connection when performing on-board writing, mount a connector on t he target system to conne ct to the dedicated flash programmer. also, incorporate a function on-board to s witch from the normal operation mode to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after rese t. therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mode, input a voltage of v ss level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, refer to 22.5.5 (1) flmd0 pin . figure 22-10. flmd0 pin connection example v850es/ke1 flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 )
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 552 (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 22-11. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/ke1 caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. table 22-7. relationship between flmd0 and flmd1 pi ns and operation mode wh en reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 553 (3) serial interface pin the following shows the pins used by each serial interface. table 22-8. pins used by serial interfaces serial interface pins used uart0 txd0, rxd0 csi00 so00, si00, sck00 csi00 +
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 554 (b) malfunction of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 22-13. malfunction of other device v850es/ke1 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/ke1 outputs affects the other device, isolate the signal on the other device side. v850es/ke1 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 555 (4) reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signal s occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 22-14. conflict of signals (reset pin) v850es/ke1 reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. (5) port pins (including nmi) when the system shifts to the flash memory programmi ng mode, all the pins that are not used for flash memory programming are in the same st atus as that immediately after rese t. if the external device connected to each port does not recognize the st atus of the port immediately after reset, pins require appropriate processing, such as connecting to v dd via a resistor or connecting to v ss via a resistor. (6) other signal pins connect x1, x2, xt1, and xt2 in the same st atus as that in the normal operation mode. (7) power supply supply the same power (v dd , v ss , ev dd , ev ss , av ss , av ref0 ) as in normal operation mode.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 556 22.5 rewriting by self programming 22.5.1 overview the v850es/ke1 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. by using this interface and a self programming library that is used to rewrit e the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, the user program c an be upgraded and constant data can be rewritten in the field. figure 22-15. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 557 22.5.2 features (1) secure self programming (boot swap function) the v850es/ke1 supports a boot swap function that ca n exchange the physical memory (blocks 0 to 3) of boot area 0 with the physical memory (blocks 4 to 7) of boot area 1. by writi ng the start program to be rewritten to boot area 1 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriti ng because the correct user program always exists in boot area 0. figure 22-16. rewriting entire memory area (boot swap) block 63 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 block 63 block 63 boot swap rewriting boot areas 0 and 1 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 (2) interrupt support instructions cannot be fetched from the flash memory during self programming. c onventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. with the v850es/ke1, a user handler can be registered to an ent ry ram area by using a library function, so that interrupt servicing can be performed by inte rnal ram or external memory execution.
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 558 22.5.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 22-17. standard self programming flow flash environment initialization processing erase processing write processing flash information setting processing note 1 internal verify processing boot area swapping processing note 2 flash environment end processing flash memory manipulation end of processing all blocks end? ? ? ?
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 559 22.5.4 flash functions table 22-9. flash function list function name outline support flashenv initialization of flash control macro
chapter 22 flash memory preliminary user?s manual u16892ej1v0ud 560 22.5.6 internal resources used the following table lists the internal resources used for se lf programming. these internal resources can also be used freely for purposes ot her than self programming. table 22-10. internal resources used resource name description entry ram area (internal ram/external ram size note ) routines and parameters used for the flash macr o service are located in this area. the entry program and default parameters are copied by calling a library initialization function. stack area (stack size note ) an extension of the stack used by the user is used by the library (can be used in both the internal ram and external ram). library code (code size note ) program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in user application execut ion status or self programming status. to use this interrupt in the self programming status, the interrupt servicing start address must be registered in advance by a registration function. nmi interrupt can be used in user application execution status or self programming status. to use this interrupt in the self programming status, the interrupt servicing start address must be registered in advance by a registration function. tm50, tm51 because tm50 and tm51 are used in the flash macro service, do not use them in the self programming status. when using tm50 and tm51 after self programming, set them again. note for the capacity to be used, refer to the v850 series flash memory se lf programming (single power supply flash memory) user?s manual (under preparation).
preliminary user?s manual u16892ej1v0ud 561 chapter 23 electrical specifications (target) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 ? 0.3 to +6.5 v ev dd v dd = ev dd = av ref0 ? 0.3 to +6.5 v av ref0 v dd = ev dd = av ref0 ? 0.3 to +6.5 v v ss v ss = ev ss = av ss ? 0.3 to +0.3 v av ss v ss = ev ss = av ss ? 0.3 to +0.3 v supply voltage ev ss v ss = ev ss = av ss ? 0.3 to +0.3 v v i1 p00 to p06, p30 to p35, p38, p39, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7, reset, flmd0 ? 0.3 to ev dd + 0.3 note v input voltage v i2 x1, x2, xt1, xt2 ? 0.3 to v dd + 0.3 note v analog input voltage v ian p70 to p77 ? 0.3 to av ref0 + 0.3 note v p00 to p06, p30 to p35, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 20 ma p38, p39 per pin 30 ma p00 to p06, p30 to p35, p38, p39, p40 to p42 35 ma output current, low i ol p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 total of all pins: 70 ma 35 ma per pin ? 10 ma p00 to p06, p30 to p35, p40 to p42 ? 30 ma output current, high i oh p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 total of all pins: ? 60 ma ? 30 ma normal operation mode ? 40 to +85 c operating ambient temperature t a flash programming mode t.b.d. c mask rom version ? 65 to +150 c storage temperature t stg flash memory version ? 40 to +125 c note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-c ollector pins, however, can be dir ectly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance stat e and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that th e absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation.
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 562 capacitance (t a = 25 ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 563 main clock oscillato r characteristics (t a = ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 564 subclock oscillator characteristics (t a = ? ? +
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 565 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (1/4) parameter symbol conditions min. typ. max. unit per pin for p00 to p06, p30 to p35, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 ? 5.0 ma ev dd = 4.0 to 5.5 v ? 30 ma total of p00 to p06, p30 to p35, p40 to p42 ev dd = 2.7 to 5.5 v ? 15 ma ev dd = 4.0 to 5.5 v ? 30 ma output current, high i oh1 total of p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 ev dd = 2.7 to 5.5 v ? 15 ma per pin for p00 to p06, p30 to p35, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 10 ma ev dd = 4.0 to 5.5 v 15 ma per pin for p38, p39 ev dd = 2.7 to 5.5 v 8 ma total of p00 to p06, p30 to p35, p40 to p42 30 ma output current, low i ol1 total of p38, p39, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 30 ma v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v v ih3 p70 to p77 0.7av ref0 av ref0 v input voltage, high v ih4 x1, x2, xt1, xt2 v dd ? 0.5 v dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v v il3 p70 to p77 av ss 0.3av ref0 v input voltage, low v il4 x1, x2, xt1, xt2 v ss 0.4 v notes 1. p00, p01, p30, p41, p98, pcm0, pcm1, pd l0 to pdl7 and their alternate-function pins. 2. reset, p02 to p06, p31 to p35, p3 8, p39, p40, p42, p50 to p55, p 90, p91, p96, p9 7, p99, p913 to p915 and their alternate-function pins.
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 566 dc characteristics (t a = ? ? ? ? ? ? ? ? ? ? ? ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 567 dc characteristics (t a = ? i dd6 stop mode subclock stopped (xt1 = v ss , when psmr.xtstp bit = 1) 0.1 30 note total current of v dd and ev dd (all ports stopped). av ref0 is not included. remark f xx : main clock frequency f x : main clock oscillation frequency f xt : subclock frequency
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 568 dc characteristics (t a = ? supply current note (
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 569 data retention characteristics stop mode (t a = ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 570 ac characteristics ac test input measurement points (v dd , av ref0 , ev dd ) ac test output measurement points load conditions v oh v ol v oh v ol measurement points dut (device under measurement) c l = 50 pf caution if the load capaci tance exceeds 50 pf due to the circ uit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. v dd 0 v v ih v il v ih v il measurement points
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 571 clkout output timing (t a = ? ? ? ? ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 572 basic operation (1) reset/external interrupt timing ( t a = ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 573 timer timing ( t a = ? ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 574 csi0 timing (1) master mode (t a = ? ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 575 so0n (output) input data output data si0n (input) sck0n (i/o) <99> <100> <100> <101> <102> <103> hi-z hi-z remarks 1. when transmit/receive type 1 (csicn.ckpn, csicn.dapn bits = 00) 2. n = 0, 1
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 576 i 2 c bus mode ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 577 i 2 c bus mode (
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 578 a/d converter (t a = ? conversion time t conv 2.7 4.0
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 579 flash memory programming characteristics (t a = ?
chapter 23 electrical specifications (target) preliminary user?s manual u16892ej1v0ud 580 flash write mode setting timing (a) serial write operation timing (uart) v dd flmd0 flmd1 0 v t dp t pr t r1 t l1 t 12 t l2 t 2c reset command reset txd0 rxd0 remark the flmd0 pulse does not have to be input for uart0 communication. (b) serial write operation timing (csi00, csi00-hs) v dd flmd0 flmd1 0 v t dp t pw t pw t pr t rp t rpe t rc reset sck00 so00 si00 reset command
preliminary user?s manual u16892ej1v0ud 581 chapter 24 package drawings 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.0 0.2 c 12.0 0.2 d f 1.125 14.0 0.2 b 12.0 0.2 n 0.10 p q 0.1 0.05 1.0 s r 3 + 4 ? 3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 + 0.06 ? 0.10 i 0.13 j k 1.0 0.2 0.65 (t.p.) l 0.5 m 0.17 + 0.03 ? 0.07 p64gk-65-9et-3 t u 0.6 0.15 0.25 f m a b cd n t l u 1.1 0.1 remark the external dimensions and materials of the es ve rsion are the same as t hose of the mass-produced version.
chapter 24 package drawings preliminary user?s manual u16892ej1v0ud 582 m 48 32 33 64 1 17 16 49 s n s j detail of lead end r k m i s l t p q g f h 64-pin plastic lqfp (10x10) item millimeters a b d g 12.0 0.2 10.0 0.2 1.25 12.0 0.2 h 0.22 0.05 c 10.0 0.2 f 1.25 i j k 0.08 0.5 (t.p.) 1.0 0.2 l 0.5 p 1.4 q 0.1 0.05 t 0.25 s 1.5 0.10 u 0.6 0.15 s64gb-50-8eu-2 r3 + 4 ? 3 n 0.08 m 0.17 + 0.03 ? 0.07 a b cd u note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. remark the external dimensions and materials of the es ve rsion are the same as t hose of the mass-produced version.
preliminary user?s manual u16892ej1v0ud 583 appendix a development tools the following development t ools are available for the development of systems that employ the v850es/ke1. figure a-1 shows the developm ent tool configuration. ? ? ? ? ? ?
appendix a development tools preliminary user?s manual u16892ej1v0ud 584 figure a-1. development tool configuration language processing software ? ? ? ? ? ? ? ?
appendix a development tools preliminary user?s manual u16892ej1v0ud 585 a.1 software package development tools (software) common to the v850 series are combined in this package. sp850 v850 series software package part number: s sp850 remark in the part number differs depending on the host machine and os used. s sp850 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler is st arted from project manager pm plus. ca850 c compiler package part number: s ca703000 df703207 (provisional name) note device file this file contains information peculiar to the device. this device file should be used in combination with a tool (ca850, sm plus, and id850qb). the corresponding os and host machine di ffer depending on the tool to be used. note under development remark in the part number differs depending on the host machine and os used. s ca703000 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom a.3 control software pm plus project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the pm plus. the pm plus is included in the c compiler package ca850. it can only be used in windows.
appendix a development tools preliminary user?s manual u16892ej1v0ud 586 a.4 debugging tools (hardware) a.4.1 when using in-circu it emulator qb-v850eskx1h qb-v850eskx1h notes 1, 2 in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using a v850es/ke1 product. it corresponds to the integrated debugger id850qb. this emulator should be used in combination with a power supply unit and emulation probe. use usb to connect this emulator to the host machine. emulation probe for gk package note 2 (part number pending) this probe is used to connect the in-circuit emulator and target system, and is designed for a 64-pin plastic tqfp (gk-9et type). emulation probe for gb package note 2 (part number pending) this probe is used to connect the in-circuit emulator and target system, and is designed for a 64-pin plastic lqfp (gb-8eu type). notes 1. qb-v850eskx1h is supplied with a power supply unit. it is also supplied with integrated debugger id850qb and a device file as control software. 2. under development
appendix a development tools preliminary user?s manual u16892ej1v0ud 587 a.5 debugging tools (software) this is a system simulator for the v850 series. the sm plus is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm plus allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. it should be used in combination with the device file (sold separately). sm plus note system simulator part number:
appendix a development tools preliminary user?s manual u16892ej1v0ud 588 a.6 embedded software the rx850 and rx850 pro are real-time oss conforming to ???? ???? ???? ???? ???? ???? ? ?
preliminary user?s manual u16892ej1v0ud 589 appendix b instruction set list b.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the re mainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the condition codes sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 590 (3) register symbols used in operations register symbol explanation
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 591 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z 0 0 1 0 z = 1 zero nz 1 0 1 0 z = 0 not zero nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) s/n 0 1 0 0 s = 1 negative ns/p 1 1 0 0 s = 0 positive t 0 1 0 1 ?
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 592 b.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2]
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 593 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 594 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 595 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2]
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 596 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 597 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2]
appendix b instruction set list preliminary user?s manual u16892ej1v0ud 598 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8.
preliminary user?s manual u16892ej1v0ud 599 appendix c register index (1/5) symbol name unit page adcr a/d conversion result register adc 339 adic interrupt control register intc 492 adm a/d converter mode register adc 336 ads analog input channel specification register adc 338 asif0 asynchronous serial interface tr ansmit status register 0 uart 360 asif1 asynchronous serial interface tr ansmit status register 1 uart 360 asim0 asynchronous serial interface mode register 0 uart 357 asim1 asynchronous serial interface mode register 1 uart 357 asis0 asynchronous serial interface status register 0 uart 359 asis1 asynchronous serial interface status register 1 uart 359 brgc0 baud rate generator control register 0 uart 378 brgc1 baud rate generator control register 1 uart 378 brgic interrupt control register intc 492 cksr0 clock select register 0 uart 377 cksr1 clock select register 1 uart 377 cmp00 8-bit timer h compare register 00 timer 282 cmp01 8-bit timer h compare register 01 timer 282 cmp10 8-bit timer h compare register 10 timer 282 cmp11 8-bit timer h compare register 11 timer 282 corad0 correction address register 0 romc 536 corad1 correction address register 1 romc 536 corad2 correction address register 2 romc 536 corad3 correction address register 3 romc 536 corcn correction control register romc 537 cr010 16-bit timer capture/compare register 010 timer 222 cr011 16-bit timer capture/compare register 011 timer 224 cr5 16-bit timer compare register 5 timer 263, 275, 278 cr50 8-bit timer compare register 50 timer 263 cr51 8-bit timer compare register 51 timer 263 crc01 capture/compare control register 01 timer 227 csi0ic0 interrupt control register intc 492 csi0ic1 interrupt control register intc 492 csic0 clocked serial interface cl ock selection register 0 csi 390 csic1 clocked serial interface cl ock selection register 1 csi 390 csim00 clocked serial interf ace mode register 00 csi 388 csim01 clocked serial interf ace mode register 01 csi 388 iic0 iic shift register 0 i 2 c 428 iicc0 iic control register 0 i 2 c 416 iiccl0 iic clock selection register 0 i 2 c 426 iicf0 iic flag register 0 i 2 c 424 iicic0 interrupt control register intc 492
appendix c register index preliminary user?s manual u16892ej1v0ud 600 (2/5) symbol name unit page iics0 iic status register 0 i 2 c 421 iicx0 iic function expansion register 0 i 2 c 427 imr0 interrupt mask register 0 intc 494 imr1 interrupt mask register 1 intc 494 imr3 interrupt mask register 3 intc 494 intf0 external interrupt falling edge specification register 0 intc 499 intf9h external interrupt falling edge specification register 9h intc 500 intr0 external interrupt rising edge specification register 0 intc 499 intr9h external interrupt rising edge specification register 9h intc 500 ispr in-service priority register intc 495 kric interrupt control register intc 492 krm key return mode register kr 513 osts oscillation stabilization time selection register standby 519 p0 port 0 register port 75 p0nfc tip00 noise elimination control register timer 216 p1nfc tip01 noise elimination control register timer 216 p3 port 3 register port 78 p4 port 4 register port 82 p5 port 5 register port 84 p7 port 7 register port 87 p9 port 9 register port 89 pcc processor clock control register cg 124 pcm port cm register port 94 pdl port dl register port 95 pf3h port 3 function register h port 80 pf4 port 4 function register port 83 pf9h port 9 function register h port 91 pfc3 port 3 function control register port 80 pfc5 port 5 function control register port 86 pfc9 port 9 function control register port 92 pfce3 port 3 function control expansion register port 80 pfm power fail comparison mode register adc 341 pft power fail comparison threshold register adc 341 pic0 interrupt control register intc 492 pic1 interrupt control register intc 492 pic2 interrupt control register intc 492 pic3 interrupt control register intc 492 pic4 interrupt control register intc 492 pic5 interrupt control register intc 492 pic6 interrupt control register intc 492 pllctl pll control register cg 129, 331 pm0 port 0 mode register port 75 pm3 port 3 mode register port 78 pm4 port 4 mode register port 82
appendix c register index preliminary user?s manual u16892ej1v0ud 601 (3/5) symbol name unit page pm5 port 5 mode register port 84 pm9 port 9 mode register port 89 pmc0 port 0 mode control register port 76 pmc3 port 3 mode control register port 79 pmc4 port 4 mode control register port 83 pmc5 port 5 mode control register port 85 pmc9 port 9 mode control register port 89 pmccm port cm mode control register port 94 pmcm port cm mode register port 94 pmdl port dl mode register port 95 prcmd command register cpu 64 prm01 prescaler mode register 01 timer 230 prscm interval timer brg compare register timer 306 prsm interval timer brg mode register timer 305 psc power save control register standby 517 psmr power save mode register standby 518 pu0 pull-up resistor option register 0 port 76 pu3 pull-up resistor option register 3 port 81 pu4 pull-up resistor option register 4 port 83 pu5 pull-up resistor option register 5 port 86 pu9 pull-up resistor option register 9 port 93 rtbh0 real-time output buffer register h0 rtp 325 rtbl0 real-time output buffer register l0 rtp 325 rtpc0 real-time output port control register 0 rtp 327 rtpm0 real-time output port mode register 0 rtp 326 rxb0 receive buffer register 0 uart 361 rxb1 receive buffer register 1 uart 361 sio00 serial i/o shift register 0 csi 395 sio01 serial i/o shift register 1 csi 395 sirb0 clocked serial interface receive buffer register 0 csi 391 sirb0l clocked serial interface re ceive buffer register 0l csi 391 sirb1 clocked serial interface receive buffer register 1 csi 391 sirb1l clocked serial interface re ceive buffer register 1l csi 391 sirbe0 clocked serial interface read -only receive buffer register 0 csi 392 sirbe0l clocked serial interface read -only receive buffer register 0l csi 392 sirbe1 clocked serial interface read -only receive buffer register 1 csi 392 sirbe1l clocked serial interface read -only receive buffer register 1l csi 392 sotb0 clocked serial interface tr ansmit buffer register 0 csi 393 sotb0l clocked serial interface tr ansmit buffer register 0l csi 393 sotb1 clocked serial interface tr ansmit buffer register 1 csi 393 sotb1l clocked serial interface tr ansmit buffer register 1l csi 393 sotbf0 clocked serial interface init ial transmit buffer register 0 csi 394 sotbf0l clocked serial interface init ial transmit buffer register 0l csi 394 sotbf1 clocked serial interface init ial transmit buffer register 1 csi 394
appendix c register index preliminary user?s manual u16892ej1v0ud 602 (4/5) symbol name unit page sotbf1l clocked serial interface init ial transmit buffer register 1l csi 394 sreic0 interrupt control register intc 492 sreic1 interrupt control register intc 492 sric0 interrupt control register intc 492 sric1 interrupt control register intc 492 stic0 interrupt control register intc 492 stic1 interrupt control register intc 492 sva0 slave address register 0 i 2 c 428 sys system status register cpu 65 tcl50 timer clock selection register 50 timer 264 tcl51 timer clock selection register 51 timer 264 tm01 16-bit timer counter 01 timer 222 tm0ic10 interrupt control register intc 492 tm0ic11 interrupt control register intc 492 tm5 16-bit timer counter 5 timer 277 tm50 8-bit timer counter 50 timer 262 tm51 8-bit timer counter 51 timer 262 tm5ic0 interrupt control register intc 492 tm5ic1 interrupt control register intc 492 tmc01 16-bit timer mode control register 01 timer 225 tmc50 8-bit timer mode control register 50 timer 265 tmc51 8-bit timer mode control register 51 timer 265 tmcyc0 8-bit timer h carrier control register 0 timer 286 tmcyc1 8-bit timer h carrier control register 1 timer 286 tmhic0 interrupt control register intc 492 tmhic1 interrupt control register intc 492 tmhmd0 8-bit timer h mode register 0 timer 284 tmhmd1 8-bit timer h mode register 1 timer 285 toc01 16-bit timer output control register 01 timer 228 tp0ccic0 interrupt control register intc 492 tp0ccic1 interrupt control register intc 492 tp0ccr0 tmp0 capture/compare register 0 timer 140 tp0ccr1 tmp0 capture/compare register 1 timer 142 tp0cnt tmp0 counter read buffer register timer 144 tp0ctl0 tmp0 control register 0 timer 134 tp0ctl1 tmp0 control register 1 timer 135 tp0ioc0 tmp0 i/o control register 0 timer 136 tp0ioc1 tmp0 i/o control register 1 timer 137 tp0ioc2 tmp0 i/o control register 2 timer 138 tp0opt0 tmp0 option register 0 timer 139 tp0ovic interrupt control register intc 492 txb0 transmit buffer register 0 uart 362 txb1 transmit buffer register 1 uart 362 vswc system wait control register cpu 66
appendix c register index preliminary user?s manual u16892ej1v0ud 603 (5/5) symbol name unit page wdcs watchdog timer clock se lection register wdt 316 wdt1ic interrupt control register intc 492 wdte watchdog timer enable register wdt 322 wdtm1 watchdog timer mode register 1 wdt 317, 497 wdtm2 watchdog timer mode register 2 wdt 321 wtic interrupt control register intc 492 wtiic interrupt control register intc 492 wtm watch timer operation mode register wt 309

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